Eprom cell

Abstract

Abstract PURPOSE:To implement a highly integrated EPROM, by arranging one control gate so as to cover both floating gate through an insulating film. CONSTITUTION:A groove is formed in a semiconductor substrate 1. Diffusion layers are provided on the lower part of the recess part of the groove and on the neighboring surfaces of the semiconductor. Thus a source 2 and drains 3 and 4 are formed. Floating gates 5 and 6 are formed on both sides of the recess part of the groove. A control gate 7 is formed so as to cover both floating gates through an insulating film. As a result, the source and the drain of a transistor having the gate 5 become 2 and 3, respectively. The source and the drain of a transistor having the gate 6 become 2 and 4, respectively.

Inventors

• 👤 Takashi Saigo
• 👤 西郷　孝

Bibliographic Details