Tunnel injection controlling type semiconductor device controlled by static induction effect

Claim 2

A tunnel injection controlling type semiconductor device, comprising: a source semiconductor region having a first conductivity type for supplying carriers; a drain semiconductor region for receiving said carriers; a gate semiconductor region for controlling a flow of said carriers, said source semiconductor region having a high impurity concentration region, said source semiconductor region containing a highly-doped semiconductor region having a second conductivity type opposite to said first conductivity type, said gate region being provided on said device at a close but separate site relative to said highly-doped semiconductor region having a second conductivity type to serve as a controlling electrode; the source and drain regions defining a main current passageway having an n ++ --p + --n--n + structure; and an insulation layer substantially surrounding the n ++ , p + and n type regions.

Claim 3

A tunnel injection controlling type semiconductor device, comprising: a source biasing electrode; a source semiconductor region (n ++ ), coupled to said source biasing electrode, supplying carriers of a first conductivity type with high impurity concentration; a drain semiconductor region (n + ) receiving carriers of the same conductivity type as in said source semiconductor region; and a channel semiconductor region provided between said source region and said drain region and containing a p + n ++ junction in which the portion coming in contact with said source region has a region having high impurity concentration of a second conductivity type opposite to said first conductivity type of said source region and the remaining portion has a region of the same conductivity type as in the source region and provides impurity concentration lower than that of the source region and in which the portion ranging from the source region to the channel region having the same conductivity type as in the source region is constructed to have a side wall, said side wall being provided with an insulation layer substantially surrounding the n ++ , p + and n type regions through which wiring is made in at least a portion of the channel region to form gate electrodes, said channel region containing the first and second conductivity types having at least a portion thereof depleted such that a tunnel injection current of carriers from the source region to the drain region may be controlled by said gate electrodes.

Claim 4

A tunnel injection controlling type semiconductor device, comprising: a source biasing electrode; a source semiconductor region (n ++ ), coupled to said source biasing electrode, supplying carriers of a first conductivity type with high impurity concentration; a drain semiconductor region (n + ) receiving carriers of the same conductivity type as in said source semiconductor region; and a channel semiconductor region provided between said source region and said drain region and containing a p + n ++ junction in which the portion coming in contact with said source region has a region having high impurity concentration of a second conductivity type opposite to said first conductivity type of said source region and the remaining portion has a region of the same conductivity type as in the source region and provides impurity concentration lower than that of the source region and in which the portion ranging from the source region to the channel region having the same conductivity type as in the source region is constructed to have a side wall, said side wall being provided with an insulation layer substantially surrounding the n ++ , p + and n type regions through which wiring is made in at least a portion of the channel region to form gate electrodes, said channel region containing the first and second conductivity types having at least a portion thereof depleted such that a tunnel injection current of carriers from the source region to the drain region may be controlled by said gate electrodes.

Claim 5

A tunnel injection controlling type semiconductor device, comprising: a source biasing electrode; a source semiconductor region (n ++ ), coupled to said source biasing electrode, supplying carriers of a first conductivity type with high impurity concentration; a drain semiconductor region (n + ) receiving carriers of the same conductivity type as in said source semiconductor region; and a channel semiconductor region provided between said source region and said drain region and containing a p + n ++ junction in which the portion coming in contact with said source region has a region having high impurity concentration of a second conductivity type opposed to said first conductivity type of said source region and the remaining portion has a region of the same conductivity type as in the source region and provides impurity concentration lower than that of the source region and in which the portion ranging from the source region to the channel region having the same conductivity type as in the source region is constructed to have a side wall, said side wall being provided with an insulation layer through which wiring is made in at least a portion of the channel region to form gate electrodes, said channel region containing the first and second conductivity types having at least a portion thereof depleted such that a tunnel injection current of carriers from the source region to the drain region may be controlled by said gate electrodes; and wherein the relationship between the impurity concentration Na and the thickness W of said region having the conductivity type opposite to that of the source region in said channel region is expressed by 9×10.sup.6 cm.sup.-1 <Na W.sup.2 <5×10.sup.7 cm.sup.-1.

Claim 6

A tunnel injection controlling type semiconductor device, comprising: a source biasing electrode; a source semiconductor region (n ++ ), coupled to said source biasing electrode, supplying carriers of a first conductivity type with high impurity concentration; a drain semiconductor region (n + ) receiving carriers of the same conductivity type as in said source semiconductor region; and a channel semiconductor region provided between said source region and said drain region and containing a p + n ++ junction in which the portion coming in contact with said source region has a region having high impurity concentration of a second conductivity type opposed to said first conductivity type of said source region and the remaining portion has a region of the same conductivity type as in the source region and provides impurity concentration lower than that of the source region and in which the portion ranging from the source region to the channel region having the same conductivity type as in the source region is constructed to have a side wall, said side wall being provided with an insulation layer through which wiring is made in at least a portion of the channel region to form gate electrodes, said channel region containing the first and second conductivity types having at least a portion thereof depleted such that a tunnel injection current of carriers from the source region to the drain region may be controlled by said gate electrodes; and wherein the relationship between the impurity concentration Na and the thickness W of said region having the conductivity type opposite to that of the source region in said channel region is expressed by 9×10.sup.6 cm.sup.-1 <Na W.sup.2 <5×10.sup.7 cm.sup.-1.

Claim 7

A tunnel injection controlling type semiconductor device, comprising: a source biasing electrode; a source semiconductor region (n ++ ), coupled to said source biasing electrode, supplying carriers of a first conductivity type with high impurity concentration; a drain semiconductor region (n) provided in a substrate of a second conductivity type in the form of three separately embedded drain regions having high impurity concentrations of the first conductivity type different from the second conductivity type; and a channel semiconductor region provided between said source region and said substrate in which the portion coming in contact with said substrate is a region having the first conductivity type with low impurity concentration and a region of the remaining portion contacting said source region has the high impurity concentration of the second conductivity type (p+) and in which the portion ranging from the source region to the low impurity concentration region is constructed to have a sidewall, on which a gate region is provided to form a floating gate structure composed of a conductive material embedded in an insulation layer and a gate electrode, said second conductivity type region of the channel region contacting the source region being formed of the middle portion having the highest impurity concentration and both sides contacting said wall and having lower impurity concentrations, said channel region containing the first and second conductivity types having at least a portion thereof almost depleted such that a tunnel injection current of carriers from the source region to the drain region may be controlled by said gate electrode.

Claim 8

A tunnel injection controlling type semiconductor device, comprising: a source biasing electrode; a source semiconductor region (n ++ ), coupled to said source biasing electrode, supplying carriers of a first conductivity type with high impurity concentration; a drain semiconductor region (n) provided in a substrate of a second conductivity type in the form of three separately embedded drain regions having high impurity concentrations of the first conductivity type different from the second conductivity type; and a channel semiconductor region provided between said source region and said substrate in which the portion coming in contact with said substrate is a region having the first conductivity type with low impurity concentration and a region of the remaining portion contacting said source region has the high impurity concentration of the second conductivity type (p+) and in which the portion ranging from the source region to the low impurity concentration region is constructed to have a sidewall, on which a gate region is provided to form a floating gate structure composed of a conductive material embedded in an insulation layer and a gate electrode, said second conductivity type region of the channel region contacting the source region being formed of the middle portion having the highest impurity concentration and both sides contacting said wall and having lower impurity concentrations, said channel region containing the first and second conductivity types having at least a portion thereof almost depleted such that a tunnel injection current of carriers from the source region to the drain region may be controlled by said gate electrode.

Claim 9

A tunnel injection controlling type semiconductor device according to claim 4, wherein the relationship between the impurity concentration Na and the thickness W of the regions having the lower impurity concentrations of the conductivity type opposite to that of the source region in said channel region is expressed by 9×10.sup.6 cm.sup.-1 <Na W.sup.2 <5×10.sup.7 cm.sup.-1.

Claim 10

A tunnel injection controlling-type semiconductor device, comprising: a highly-doped source semiconductor region having a first conductivity type for supplying carriers; a highly-doped drain semiconductor region having a second conductivity type opposite to said first conductivity type for receiving said carriers; a channel semiconductor region having said second conductivity type disposed between said source region and said drain region in which the portion adjacent to said source region is highly-doped and the carrier concentration of the remaining part is lower than in said highly-doped portion of said channel region, said highly-doped portion of said channel region between said source region and said drain region having a thickness of less than 0.2 microns; and a gate structure disposed adjacent to at least a portion of said channel region for controlling tunnel current flow from said source region to said drain region.

Claim 11

A tunnel injection controlling-type semiconductor device, comprising: a highly-doped source semiconductor region having a first conductivity type for supplying carriers; a highly-doped drain semiconductor region having a second conductivity type opposite to said first conductivity type for receiving said carriers; a channel semiconductor region having said second conductivity type disposed between said source region and said drain region in which the portion adjacent to said source region is highly-doped and the carrier concentration of the remaining part is lower than in said highly-doped portion of said channel region, said highly-doped portion of said channel region between said source region and said drain region having a thickness of less than 0.2 microns; and a gate structure disposed adjacent to at least a portion of said channel region for controlling tunnel current flow from said source region to said drain region.

Claim 12

A device as in claim 6, wherein the proximal distance between said source region and said drain region is less than 3 microns.

Claim 13

A device as in claim 6 wherein said highly-doped portion of said channel region having a thickness of less than 0.2 microns extends no more than 2 microns from said gate.

Claim 14

A device as in claim 8 wherein the proximal distance between said source region and said drain region is less than 3 microns.

Claim 15

A tunnel injection controlling-type semiconductor device, comprising: a highly-doped source semiconductor region having a first conductivity type for supplying carriers; a highly-doped drain semiconductor region having a second conductivity type opposite to said first conductivity type for receiving said carriers; a channel semiconductor region having said second conductivity type disposed between said source region and said drain region in which the portion adjacent to said source region is highly-doped and the carrier concentration of the remaining part is lower than in said highly-doped portion of said channel region, wherein the relationship between the impurity concentration Na and the thickness W of said highly doped region adjacent to said source region is expressed by 9×10 6 cm -1 <Na W 2 <5×10 7 cm -1 ; and a gate structure disposed adjacent to at least a portion of said channel region for controlling tunnel current flow from said location substantially adjacent to the junction between said channel region and said source region.

Claim 16

A tunnel injection controlling-type semiconductor device, comprising: a highly-doped source semiconductor region having a first conductivity type for supplying carriers; a highly-doped drain semiconductor region having a second conductivity type opposite to said first conductivity type for receiving said carriers; a channel semiconductor region having said second conductivity type disposed between said source region and said drain region in which the portion adjacent to said source region is highly-doped and the carrier concentration of the remaining part is lower than in said highly-doped portion of said channel region, wherein the relationship between the impurity concentration Na and the thickness W of said highly doped region adjacent to said source region is expressed by 9×10 6 cm -1 <Na W 2 <5×10 7 cm -1 ; and a gate structure disposed adjacent to at least a portion of said channel region for controlling tunnel current flow from said location substantially adjacent to the junction between said channel region and said source region.