US4926224A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Crosspoint dynamic ram cell for folded bitline array
Assignee: Texas Instruments Inc
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Filing: 1989-03-06
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Granted: 1990-05-15
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Expires: 2009-03-06
Abstract
Abstract A dynamic random access memory cell array is disclosed which has storage capacitors and access transistors formed on the sidewalls of pillars created by trenches etched into the face of a semiconductor bar. A storage capacitor for a cell uses the sidewalls of the pillar as one plate and a polysilicon plug or web as the other plate. The channel of each access transistor is formed in the upper part of the sidewall of only a portion of the pillar, using an upper edge of the capacitor region as the source region of the transistor and having an N+ drain region at the top of the pillar. A cross-point array is made possible by merging two adjacent wordlines as a pair of overlying conductor strips extending along the face over the trenches, between pillars, and forming the transistor gates by alternate protrusions from these strips, extending down into the trenches at the channel area.
Inventors
- 👤 Donald J. Redwine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:41
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665; Y; Y10; Y10S; Y10S257/00; Y10S257/922; Y10S257/929
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
180 words
A dynamic random access memory cell formed on a semiconductor body having an upper surface and a trench region formed therein, the trench region including a trench upper portion extending toward the upper surface and a trench lower portion extending away from the upper surface into the semiconductor body, said cell comprising: a transistor including a first source/drain region formed on the upper semiconductor surface and a channel region formed in the semiconductor body along the trench upper portion; a first capacitor region formed in the trench lower portion; a second capacitor region formed in the semiconductor body adjacent the first capacitor region and extending toward the transistor channel region; an insulative layer position between said first and second capacitor regions to provide electrical isolation between said regions; and a pair of overlapping conductive layers electrically isolated from one another each layer extending along the upper surface of the semiconductor body adjacent the first source/drain region, one of said layers including a segment protruding into the trench upper portion along the channel region forming a control gate for the transistor.
Claim 2
Dependent Claim
180 words
A dynamic random access memory cell formed on a semiconductor body having an upper surface and a trench region formed therein, the trench region including a trench upper portion extending toward the upper surface and a trench lower portion extending away from the upper surface into the semiconductor body, said cell comprising: a transistor including a first source/drain region formed on the upper semiconductor surface and a channel region formed in the semiconductor body along the trench upper portion; a first capacitor region formed in the trench lower portion; a second capacitor region formed in the semiconductor body adjacent the first capacitor region and extending toward the transistor channel region; an insulative layer position between said first and second capacitor regions to provide electrical isolation between said regions; and a pair of overlapping conductive layers electrically isolated from one another each layer extending along the upper surface of the semiconductor body adjacent the first source/drain region, one of said layers including a segment protruding into the trench upper portion along the channel region forming a control gate for the transistor.
Claim 3
Dependent Claim
13 words
The cell of claim 1 wherein the first capacitor region comprises polysilicon material.
Claim 4
Dependent Claim
22 words
The cell of claim 1 wherein the second capacitor region undergoes inversion when a voltage is applied to the first capacitor region.
Claim 5
Dependent Claim
22 words
The cell of claim 1 further including a bit line extending over said conductive layers and over the first source drain region.
Claim 6
Dependent Claim
30 words
The cell according to claim 1 wherein the trench region defines a semiconductor pillar on which the first source/drain region, the channel region and the second capacitor region are formed.
Claim 7
Dependent Claim
107 words
The cell according to claim 5 wherein: the trench region defines a plurality of additional semiconductor pillars arranged in rows and columns along the upper surface of the semiconductor body, the first capacitor region extending about the plurality of pillar thereby forming a conductive web, each pillar including a transistor and a second capacitor region, the combination forming a crosspoint array of memory cells; and the pair of overlapping conductive layers forms wordlines for a column of cells, each of said layers including a segment protruding into the trench upper portion along the channel region to form a control gate for a different transistor in the column.
Claim 8
Dependent Claim
47 words
The cell according to claim 6 wherein each of the overlapping layers includes a plurality of segments protruding into the trench upper portion to form control gates for the column of cells, protruding segments from different layers alternately arranged to simultaneously control conduction in alternate cell transistors.
Claim 9
Dependent Claim
23 words
The cell according to claim 1 wherein the semiconductor body comprises a single crystal silicon and the first conductive region comprises polycrystalline silicon.
Claim 10
Dependent Claim
22 words
The cell according to claim 1 wherein a portion of the second capacitor region includes a second source/drain region for the transistor.
Claim 11
Dependent Claim
21 words
The cell according to claim 9 wherein the semiconductor body is predominately P-type silicon and the source/drain regions are N+ silicon.
Claim 12
Dependent Claim
176 words
A memory device of the type formed with an array of cells, each cell including a transistor coupled to a storage capacitor, said device comprising: a semiconductor body having an upper surface and a plurality of trench regions formed therein, each trench region including a trench upper portion extending toward the semiconductor upper surface and a trench lower portion extending away from the upper surface and into the semiconductor body; an array of one transistor memory cells each including a first source/drain region formed on the upper semiconductor surface and a channel region formed along a trench upper portion, a first capacitor region formed in the trench lower portion, a second capacitor region formed in the semiconductor body adjacent the first capacitor region and extending toward the transistor channel region and an insulative layer positioned to provide electrical isolation between said first and second capacitor regions; and a pair of overlapping conductive layers electrically isolated from one another and extending along the upper surface of the semiconductor body adjacent a first plurality of the memory cells.
Claim 13
Dependent Claim
176 words
A memory device of the type formed with an array of cells, each cell including a transistor coupled to a storage capacitor, said device comprising: a semiconductor body having an upper surface and a plurality of trench regions formed therein, each trench region including a trench upper portion extending toward the semiconductor upper surface and a trench lower portion extending away from the upper surface and into the semiconductor body; an array of one transistor memory cells each including a first source/drain region formed on the upper semiconductor surface and a channel region formed along a trench upper portion, a first capacitor region formed in the trench lower portion, a second capacitor region formed in the semiconductor body adjacent the first capacitor region and extending toward the transistor channel region and an insulative layer positioned to provide electrical isolation between said first and second capacitor regions; and a pair of overlapping conductive layers electrically isolated from one another and extending along the upper surface of the semiconductor body adjacent a first plurality of the memory cells.
Claim 14
Dependent Claim
36 words
The device of claim 11 wherein each of said layers is a word line comprising segments protruding into trench upper portions to form control gates for transistor channel regions of the first plurality of memory cells.
Claim 15
Dependent Claim
42 words
The device of claim 12 wherein: the first plurality of memory cells forms a row in the array of cells; and control gates associated with each word line are alternately arranged such that each word line controls alternate cells along the row.
Claim 16
Dependent Claim
25 words
The device of claim 11 wherein trench regions are interconnected to define a plurality of pillars on and about which the memory cells are formed.
Claim 17
Dependent Claim
102 words
The device of claim 11 wherein: the first plurality of memory cells forms a row in the array of cells; each of said layers is a word line comprising segments protruding into trench upper portions to form control gates for transistor channel regions of the first plurality of memory cells; control gates associated with each word line are alternately arranged such that each word line controls alternate cells along the row; trench regions are interconnected to define a plurality of pillars on and about which memory cells are formed; and the first capacitor regions of each cell in the row are interconnected.
Claim 18
Dependent Claim
25 words
The device of claim 15 wherein the semiconductor body predominately comprises lightly doped monocrystalline silicon and the first capacitor regions are formed of polycrystalline silicon.
Claim 19
Dependent Claim
77 words
The device of claim 15 wherein the array of cells is arranged in rows and columns said device comprising a bit line along each column and a plurality of additional pairs of overlapping wordlines each pair extending along a row of the array, wordlines of each pair connected to gates of alternate cells in a row thereby providing a crosspoint array with a memory cell positioned at the crossing of each bit line and word line pair.
Claim 20
Dependent Claim
98 words
A memory device of the type formed with an array of memory cells wherein each cell includes a transistor; said device comprising: a plurality of bit lines and a plurality of pairs of overlapping word lines crossing the bit lines; memory cells positioned at crossings of bit lines and word line pairs to form rows and columns of cells, each memory cell comprising a transistor having a channel region and a gate for controlling conduction through the channel region, word lines of a pair connected to gates of alternate ones of said transistors along a row of cells.
Claim 21
Dependent Claim
98 words
A memory device of the type formed with an array of memory cells wherein each cell includes a transistor; said device comprising: a plurality of bit lines and a plurality of pairs of overlapping word lines crossing the bit lines; memory cells positioned at crossings of bit lines and word line pairs to form rows and columns of cells, each memory cell comprising a transistor having a channel region and a gate for controlling conduction through the channel region, word lines of a pair connected to gates of alternate ones of said transistors along a row of cells.
Claim 22
Dependent Claim
47 words
The device of claim 18 wherein, for the plurality of wordline paris, wordlines of each pair are alternately connected to transistor gates in a row to provide a cross point array with a memory cell at each crossing of a bit line and a word line pair.
Claim 23
Dependent Claim
22 words
The device of claim 19 wherein adjacent pairs of bit lines are connected to sense amplifiers in a folded bit line configuration.
Claim 24
Dependent Claim
33 words
The device according to claim 34 wherein each of said cells comprises a storage capacitor coupled to a transistor source region, each cell transistor including a source-to-drain path coupled to a bit line.
Claim 25
Dependent Claim
142 words
The device of claim 18 wherein: each of said cells is formed along a semiconductor body having an upper surface and a plurality of trench regions formed therein, each trench region including a trench upper portion extending toward the semiconductor upper surface and a trench lower portion extending away from the upper surface and into the semiconductor body; each memory cell includes a first source/drain region formed on the upper semiconductor surface, a first capacitor region formed in the trench lower portion and a second capacitor region formed in the semiconductor body adjacent the first capacitor region; and for each cell a transistor channel region is formed along a trench upper portion with the first capacitor region extending toward the transistor channel region, each cell further including an insulative layer positioned to provide electrical isolation between said first and second capacitor regions.
Claim 26
Dependent Claim
41 words
The device of claim 22 wherein trench regions are interconnected to define a plurality of pillars each extending from a trench lower portion to the upper surface of the semiconductor body and wherein memory cells are formed on and about pillars.
Claim 27
Dependent Claim
16 words
The device of claim 22 wherein the first capacitor region of each cell surrounds a pillar.
Claim 28
Dependent Claim
26 words
The device of claim 22 wherein trench regions are interconnected and the first capacitor regions are interconnected along the trench regions to form a conductive web.
Claim 29
Dependent Claim
22 words
The device of claim 22 wherein adjacent pairs of bit lines are connected to sense amplifiers in a folded bit line configuration.
Claim 30
Dependent Claim
26 words
The device of claim 22 wherein for each memory cell the second capacitor region undergoes inversion when a voltage is applied to the first capacitor region.
Claim 31
Dependent Claim
35 words
The device according to claim 18 wherein the memory cells are formed in a semiconductor body predominately comprising lightly doped monocrystalline silicon, the first capacitor regions comprise polysilicon and the cell transistors are N-channel type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |