US6124729A
Expired / Lapsed
US
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Field programmable logic arrays with vertical transistors
Assignee: Micron Technology Inc
•
Filing: 1998-02-27
•
Granted: 2000-09-26
•
Expires: 2018-02-27
Abstract
Abstract A field programmable logic array with vertical transistors having single or split control lines is used to provide logical combinations responsive to an input signal. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the field programmable logic array. The field programmable logic array is programmed in the field to select a particular logic combination responsive to a received input signal. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F 2 is needed per bit of logic, where F is the minimum lithographic feature size.
Inventors
- 👤 Wendell P. Noble
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:22
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/1778; H03K19/17796; H10B; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B69/00
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
156 words
A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes: at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistors, and a number of floating gates wherein each floating gate is associated with a side of the pillar, and a number of control lines wherein each control line is associated with a floating gate.
Claim 2
Dependent Claim
156 words
A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes: at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistors, and a number of floating gates wherein each floating gate is associated with a side of the pillar, and a number of control lines wherein each control line is associated with a floating gate.
Claim 3
Dependent Claim
26 words
The programmable logic array of claim 1, wherein each one of the control lines in the first logic plane interconnects with one of the input lines.
Claim 4
Dependent Claim
33 words
The programmable logic array of claim 2, wherein each one of the control lines in the second logic plane interconnects with one of the source and drain regions in the first logic plane.
Claim 5
Dependent Claim
18 words
The programmable logic array of claim 1, wherein there are two independent control lines between two common pillars.
Claim 6
Dependent Claim
27 words
The programmable logic array of claim 1, wherein the first logic plane is an AND logic plane and the second logic plane is an OR logic plane.
Claim 7
Dependent Claim
27 words
The programmable logic array of claim 1, wherein the first logic plane is a NOR logic plane and the second logic plane is a NOR logic plane.
Claim 8
Dependent Claim
33 words
The programmable logic array of claim 1, wherein the transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between the source regions and the drain regions.
Claim 9
Dependent Claim
14 words
The programmable logic array of claim 1, wherein the substrate is a bulk semiconductor.
Claim 10
Dependent Claim
25 words
The programmable logic array of claim 1, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.
Claim 11
Dependent Claim
19 words
The programmable logic array of claim 1, wherein the programmable logic array is operatively coupled to a computer system.
Claim 12
Dependent Claim
165 words
A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a first array coupled to the plurality of input lines, the first array having a plurality of logic cells arranged in rows and columns for providing a first term responsive to the received input signal; a second array having a plurality of logic cells arranged in rows and columns for receiving the first term and providing a second term responsive to the first term; and a plurality of output lines for receiving the second term, wherein each logic cell includes: at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistors, and a number of floating gates wherein each gate is associated with a side of the pillar, and a number of control lines wherein each control line is associated with a floating gate.
Claim 13
Dependent Claim
165 words
A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a first array coupled to the plurality of input lines, the first array having a plurality of logic cells arranged in rows and columns for providing a first term responsive to the received input signal; a second array having a plurality of logic cells arranged in rows and columns for receiving the first term and providing a second term responsive to the first term; and a plurality of output lines for receiving the second term, wherein each logic cell includes: at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistors, and a number of floating gates wherein each gate is associated with a side of the pillar, and a number of control lines wherein each control line is associated with a floating gate.
Claim 14
Dependent Claim
23 words
The programmable logic array of claim 11, wherein the first term is a product term and the second term is a sum term.
Claim 15
Dependent Claim
23 words
The programmable logic array of claim 11, wherein the first term is a sum term and the second term is a product term.
Claim 16
Dependent Claim
25 words
The programmable logic array of claim 11, wherein each one of the control lines of the first array interconnects with one of the input lines.
Claim 17
Dependent Claim
31 words
The programmable logic array of claim 14, wherein each one of the control lines of the second array interconnects with one of the source and drain regions of the first array.
Claim 18
Dependent Claim
18 words
The programmable logic array of claim 11, wherein there are two independent control lines between two common pillars.
Claim 19
Dependent Claim
33 words
The programmable logic array of claim 11, wherein the transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between the source regions and the drain regions.
Claim 20
Dependent Claim
14 words
The programmable logic array of claim 11, wherein the substrate is a bulk semiconductor.
Claim 21
Dependent Claim
25 words
The programmable logic array of claim 11, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.
Claim 22
Dependent Claim
19 words
The programmable logic array of claim 11, wherein the programmable logic array is operatively coupled to a computer system.
Claim 23
Dependent Claim
145 words
A programmable logic array, comprising: an array of logic cells, each logic cell including at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that forms source, drain, and body regions for the transistors and at least a pair of floating gates disposed adjacent to the opposing sides of the pillar; at least one first source and drain interconnection line, interconnecting one of the first source and drain regions of one of the logic cells; a plurality of output lines, each output line interconnecting one of the second source and drain regions of ones of the logic cells; and a plurality of input lines for receiving an input signal, wherein the array of logic cells connected between the plurality of input lines and the plurality of output lines provides a logical combination responsive to the received input signal.
Claim 24
Dependent Claim
145 words
A programmable logic array, comprising: an array of logic cells, each logic cell including at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that forms source, drain, and body regions for the transistors and at least a pair of floating gates disposed adjacent to the opposing sides of the pillar; at least one first source and drain interconnection line, interconnecting one of the first source and drain regions of one of the logic cells; a plurality of output lines, each output line interconnecting one of the second source and drain regions of ones of the logic cells; and a plurality of input lines for receiving an input signal, wherein the array of logic cells connected between the plurality of input lines and the plurality of output lines provides a logical combination responsive to the received input signal.
Claim 25
Dependent Claim
18 words
The programmable logic array of claim 21, wherein there are two independent input lines between two common pillars.
Claim 26
Dependent Claim
33 words
The programmable logic array of claim 21, wherein the transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between the source regions and the drain regions.
Claim 27
Dependent Claim
17 words
The programmable logic array of claim 21, wherein the pillar extends outwardly from a bulk semiconductor substrate.
Claim 28
Dependent Claim
25 words
The programmable logic array of claim 21, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.
Claim 29
Dependent Claim
19 words
The programmable logic array of claim 21, wherein the programmable logic array is operatively coupled to a computer system.
Claim 30
Dependent Claim
175 words
A computer system, the computer system comprising a programmable logic array, the programmable logic array including: a plurality of input lines for receiving an input signal; a first array coupled to plurality of input lines, the first array having a plurality of logic cells arranged in rows and columns for providing a first term responsive to the received input signal; a second array having a plurality of logic cells arranged in rows and columns for receiving the first term and providing a second term responsive to the first term; and a plurality of output lines for receiving the second term, wherein each logic cell includes: at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistors, and a number of floating gates wherein each gate is associated with a side of the pillar, and a number of control lines wherein each control line is associated with a floating gate.
Claim 31
Dependent Claim
175 words
A computer system, the computer system comprising a programmable logic array, the programmable logic array including: a plurality of input lines for receiving an input signal; a first array coupled to plurality of input lines, the first array having a plurality of logic cells arranged in rows and columns for providing a first term responsive to the received input signal; a second array having a plurality of logic cells arranged in rows and columns for receiving the first term and providing a second term responsive to the first term; and a plurality of output lines for receiving the second term, wherein each logic cell includes: at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistors, and a number of floating gates wherein each gate is associated with a side of the pillar, and a number of control lines wherein each control line is associated with a floating gate.
Claim 32
Dependent Claim
22 words
The computer system of claim 27, wherein the first term is a product term and the second term is a sum term.
Claim 33
Dependent Claim
22 words
The computer system of claim 27, wherein the first term is a sum term and the second term is a product term.
Claim 34
Dependent Claim
24 words
The computer system of claim 27, wherein each one of the control lines of the first array interconnects with one of the input lines.
Claim 35
Dependent Claim
30 words
The computer system of claim 27, wherein each one of the control lines of the second array interconnects with one of the source and drain regions of the first array.
Claim 36
Dependent Claim
17 words
The computer system of claim 27, wherein there are two independent control lines between two common pillars.
Claim 37
Dependent Claim
32 words
The computer system of claim 27, wherein the transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between the source regions and the drain regions.
Claim 38
Dependent Claim
13 words
The computer system of claim 27, wherein the substrate is a bulk semiconductor.
Claim 39
Dependent Claim
24 words
The computer system of claim 27, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-26 | 2004-03-27 | 2004-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-26 | 2008-03-27 | 2008-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-26 | 2012-03-27 | 2012-09-26 | $7700.00 | Window Closed / Lapsed |