Vertical transistor having an underlying gate electrode contact

Claim 1

A transistor comprising: a substrate formed of a semiconductor material; a dielectric layer formed overlying the substrate and having a first portion of an opening which exposes a portion of the substrate to form an exposed substrate portion; a conductive interconnect layer formed overlying the dielectric layer, the conductive layer having a second portion of an opening horizontally aligned with the first portion of the opening; a vertically raised region made of the semiconductor material and overlying the exposed substrate portion and lying within the first portion and second portion of the opening, the vertically raised region having a first electrode, a second electrode overlying the first electrode, and a channel region separating the first electrode and the second electrode; a gate electrode dielectric layer formed adjacent the channel region and overlying the conductive interconnect layer; a gate electrode formed overlying the conductive interconnect layer and being laterally adjacent the gate electrode dielectric layer for selectively altering a current flow through the channel region in response to a voltage applied to the gate electrode; and a contact region wherein a bottom portion of the gate electrode contacts a top portion of the conductive interconnect layer.