Thin film transistor having a self-aligned gate underlying a channel region

Claim 2

An under-gated thin film transistor comprising: an insulated substrate having a surface with a stacked structure including a first gate electrode overlying the substrate surface and a gate dielectric layer overlying the first gate electrode, the first gate electrode having a first edge, a second edge, and a top surface; a planar layer adjacent to the first gate electrode and adjacent to the gate dielectric layer, the planar layer having a sidewall which extends above the first gate electrode, the sidewall being substantially perpendicular to the top surface of the first gate electrode and defining an opening overlying the first gate electrode; a conductive layer overlying the gate dielectric layer, the conductive layer having a first portion within the opening and a second portion outside of the opening; a drain region within the second portion of the conductive layer, the drain region is aligned to the sidewall of the planar layer, and offset from the first gate electrode by a predetermined distance; and a source region contained within a part of the second portion of the conductive layer, the source region is aligned to the the sidewall of the planar layer; a channel region within the conductive layer between the source region and the drain region, the channel region being formed only within the first portion of the conductive layer, a portion of the channel region underlying a portion of the source region.

Claim 3

The thin film transistor of claim 1 wherein the sidewall of the planar layer has an adjacent sidewall spacer formation.

Claim 4

The thin film transistor of claim 1 wherein the first gate electrode and the conductive layer are made of polysilicon.

Claim 5

The thin film transistor of claim 1 wherein the source region is offset from the first gate electrode by a predetermined distance.

Claim 6

The thin film transistor of claim 1 wherein the planar layer comprises a material selected from a group consisting of: a spin on glass (SOG) and an oxide having a planar surface.

Claim 7

The thin film transistor of claim 1 further comprising a sidewall spacer formed directly overlying the gate dielectric layer.

Claim 8

The thin film transistor of claim 1 wherein an etch stop layer overlies the conductive layer.

Claim 9

The thin film transistor of claim 1 wherein the gate dielectric layer is formed of a material selected from a group consisting of: a silicon dioxide material and a nitride material.

Claim 10

The thin film transistor of claim 1 further comprising: a plug region overlying the first portion of the conductive layer, the plug region being adjacent both the source region and the drain region.

Claim 11

The thin film transistor of claim 7 wherein the plug region comprises a material selected from a group consisting of: a polysilicon material, a tetraethylorthosilicate (TEOS) material, a borophosphosilicate glass (BPSG) material, a spin on glass (SOG), and a nitride material.

Claim 12

The thin film transistor of claim 1 wherein a second gate electrode is formed overlying the conductive layer.

Claim 13

The thin film transistor of claim 1 wherein a doped dielectric is formed adjacent the conductive layer, the doped dielectric layer containing dopant atoms, the dopant atoms being a same type of dopant atoms used to form said source region and said drain region.

Claim 14

An under-gated thin film transistor comprising: a substrate having a surface; a first gate electrode having a first edge and a second edge overlying the substrate; a gate dielectric layer overlying the first gate electrode; a planar dielectric layer formed adjacent the first gate electrode and adjacent the gate dielectric layer, the planar dielectric layer having an opening with a sidewall, the opening overlying which overlies the first gate electrode; a conductive layer overlying the gate dielectric layer and the planar dielectric layer, the conductive layer having a first portion within the opening and a second portion outside the opening; a drain region formed within a part of the second portion of the conductive layer, the drain region being aligned to the sidewall of the opening; a source region formed within a part of the second portion of the conductive layer, the source region being aligned to the sidewall of the opening; a channel region defined within the conductive layer, the channel region physically separating the source region from the drain region and; an offset region within the conductive layer, the offset region overlying a portion of the channel region and being between the drain region and the channel region.

Claim 15

An under-gated thin film transistor comprising: a substrate having a surface; a first gate electrode having a first edge and a second edge overlying the substrate; a gate dielectric layer overlying the first gate electrode; a planar dielectric layer formed adjacent the first gate electrode and adjacent the gate dielectric layer, the planar dielectric layer having an opening with a sidewall, the opening overlying which overlies the first gate electrode; a conductive layer overlying the gate dielectric layer and the planar dielectric layer, the conductive layer having a first portion within the opening and a second portion outside the opening; a drain region formed within a part of the second portion of the conductive layer, the drain region being aligned to the sidewall of the opening; a source region formed within a part of the second portion of the conductive layer, the source region being aligned to the sidewall of the opening; a channel region defined within the conductive layer, the channel region physically separating the source region from the drain region and; an offset region within the conductive layer, the offset region overlying a portion of the channel region and being between the drain region and the channel region.

Claim 16

The thin film transistor of claim 13 wherein a sidewall spacer is formed adjacent the opening in the planar dielectric layer.

Claim 17

The thin film transistor of claim 13 wherein an etch stop layer overlies the conductive layer.

Claim 18

The thin film transistor of claim 13 further comprising a plug region overlying the conductive layer and adjacent said source region and said drain region.

Claim 19

The thin film transistor of claim 13 wherein a second gate electrode is formed overlying the conductive layer.

Claim 20

The thin film transistor of claim 13 wherein a doped dielectric is formed adjacent the conductive layer, the doped dielectric layer having dopant atoms which are identical to the dopant atoms used to form said source region and said drain region.

Claim 21

An under-gated thin film transistor comprising: a silicon substrate having a surface; a polysilicon gate electrode having a first edge and a second edge overlying the silicon substrate; a gate dielectric layer overlying the polysilicon gate electrode; a planarized dielectric layer formed adjacent the polysilicon gate electrode and adjacent the gate dielectric layer, the planarized dielectric layer having an opening which overlies the gate dielectric layer, the opening having a first sidewall which is vertically aligned to the first edge and a second sidewall which is vertically aligned to the second edge; a polysilicon layer overlying the gate dielectric layer and being formed at least partially within said opening; a plug region formed both overlying the polysilicon layer and within a portion of said opening; a drain region formed within a first portion of the polysilicon layer and being aligned to the first sidewall of the opening, the drain region being offset from the polysilicon gate electrode by a predetermined distance; a source region formed within a second portion of the polysilicon layer and being aligned to the second sidewall of the opening, the source region being offset from the polysilicon gate electrode by a predetermined distance; and a channel region defined within the polysilicon layer, the channel region physically separating the source region from the drain region, underlying a portion of the plug region, and having a length which is defined by the opening, the channel region lying entirely within the opening.

Claim 22

An under-gated thin film transistor comprising: a silicon substrate having a surface; a polysilicon gate electrode having a first edge and a second edge overlying the silicon substrate; a gate dielectric layer overlying the polysilicon gate electrode; a planarized dielectric layer formed adjacent the polysilicon gate electrode and adjacent the gate dielectric layer, the planarized dielectric layer having an opening which overlies the gate dielectric layer, the opening having a first sidewall which is vertically aligned to the first edge and a second sidewall which is vertically aligned to the second edge; a polysilicon layer overlying the gate dielectric layer and being formed at least partially within said opening; a plug region formed both overlying the polysilicon layer and within a portion of said opening; a drain region formed within a first portion of the polysilicon layer and being aligned to the first sidewall of the opening, the drain region being offset from the polysilicon gate electrode by a predetermined distance; a source region formed within a second portion of the polysilicon layer and being aligned to the second sidewall of the opening, the source region being offset from the polysilicon gate electrode by a predetermined distance; and a channel region defined within the polysilicon layer, the channel region physically separating the source region from the drain region, underlying a portion of the plug region, and having a length which is defined by the opening, the channel region lying entirely within the opening.

Claim 23

The thin film transistor of claim 19 wherein a sidewall spacer is formed adjacent the opening in the planarized dielectric layer.