Self-aligned semiconductor devices

Claim 2

A process for fabricating semiconductor devices on a major surface of a semiconductor substrate provided with suitably doped regions therein, including: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said surface, said structure including a buried etch-stop layer sandwiched between dielectric layers; (c) using a mask in conjunction with a resist layer formed on said multi-layer structure and etching of undesired portions thereof to define a plurality of slots corresponding to various elements of said devices, thereby self-aligning said elements with each other; (d) filling said slots with a conducting material and forming N and P regions in said substrate by implanting ions in regions underlying said slots; (e) removing upper portions of said conducting material where no contact thereto is desired; and (f) forming a metallic layer thereover to contact portions of said conducting material where contact is desired.

Claim 3

The process of claim 1 wherein after removing said upper portions of said conducting material, said resulting structure is planarized by filling any open regions with a planarizing material, leaving the surface of portions of conducting material to be contacted in the same plane as that of said planarizing material and wherein said metallic layer is then formed on said planarizing material to contact said portions of said conducting material in the same plane as that of said planarizing material.

Claim 4

The process of claim 1 wherein said multi-layer structure comprises: (a) a first layer consisting essentially of a field oxide; (b) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said field oxide; (c) a third layer consisting essentially of an oxide; and (d) a fourth layer consisting essentially of a material having an etch rate significantly different than said field oxide.

Claim 5

The process of claim 3 wherein said fourth layer comprises a material selected from the group consisting of polysilicon and silicon nitride.

Claim 6

The process of claim 1 wherein said conducting material comprises a material selected from the group consisting of polysilicon and tungsten.

Claim 7

The process of claim 5 wherein said conducting material consists essentially of polysilicon and said slots are filled with said polysilicon and said N and P regions are formed in said substrate by implanting ions into said polysilicon in said slots.

Claim 8

The process of claim 5 wherein said conducting material consists essentially of tungsten and said N and P regions are formed in said substrate by implanting ions thereinto through said slots and said slots are then filled with tungsten.

Claim 9

A process for forming a self-aligned planarized semiconductor device comprising a plurality of elements and formed in a major surface of a semiconductor, comprising: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said semiconductor surface, said multi-layer structure including at least one etch-stop layer; (c) using a slot mask in conjunction with a resist layer formed on said multi-layer structure to lithographically define a plurality of slots corresponding to various elements of said devices, thereby self-aligning said elements with each other; (d) etching portions of said multi-layer structure corresponding to said slots, stopping at said etch-stop layer; (e) stripping said resist layer; (f) using an active mask in conjunction with another resist layer formed on said multi-layer structure to define said active area encompassing a group of said slots associated with said active area of an individual device; (g) removing any remaining portions of said multi-layer structure in said slots; (h) filling said slots with a conducting material to form conducting plugs and forming N and P regions in said substrate by implanting ions in regions underlying said slots; (i) planarizing said plugs to the surface of said multi-layer structure; (j) applying a connector mask to expose portions of said multi-layer structure between at least some of said elements; (k) etching exposed portions of said third layer back to said buried etch-stop layer; and (l) etching exposed portions of said etch-stop layer to said field oxide layer.

Claim 10

A process for forming a self-aligned planarized semiconductor device comprising a plurality of elements and formed in a major surface of a semiconductor, comprising: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said semiconductor surface, said multi-layer structure including at least one etch-stop layer; (c) using a slot mask in conjunction with a resist layer formed on said multi-layer structure to lithographically define a plurality of slots corresponding to various elements of said devices, thereby self-aligning said elements with each other; (d) etching portions of said multi-layer structure corresponding to said slots, stopping at said etch-stop layer; (e) stripping said resist layer; (f) using an active mask in conjunction with another resist layer formed on said multi-layer structure to define said active area encompassing a group of said slots associated with said active area of an individual device; (g) removing any remaining portions of said multi-layer structure in said slots; (h) filling said slots with a conducting material to form conducting plugs and forming N and P regions in said substrate by implanting ions in regions underlying said slots; (i) planarizing said plugs to the surface of said multi-layer structure; (j) applying a connector mask to expose portions of said multi-layer structure between at least some of said elements; (k) etching exposed portions of said third layer back to said buried etch-stop layer; and (l) etching exposed portions of said etch-stop layer to said field oxide layer.

Claim 11

The process of claim 8 wherein said multi-layer structure comprises: (a) a first layer consisting essentially of a field oxide; (b) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said field oxide; (c) a third layer consisting essentially of an oxide; and (d) a fourth layer consisting essentially of a material having an etch rate significantly different than said field oxide.

Claim 12

The process of claim 9 wherein said fourth layer comprises a material selected from the group consisting of polysilicon and silicon nitride.

Claim 13

The process of claim 9 further including implanting dopant species through exposed portions of said field oxide layer to form channel regions between at least some of said elements.

Claim 14

The process of claim 8 wherein said conducting material comprises a material selected from the group consisting of polysilicon and tungsten.

Claim 15

The process of claim 12 wherein said conducting material consists essentially of polysilicon and said slots are filled with said polysilicon and said N and P regions are formed in said substrate by implanting ions into said polysilicon in said slots.

Claim 16

The process of claim 12 wherein said conducting material consists essentially of tungsten and said N and P regions are formed in said substrate by implanting ions thereinto through said slots and said slots are then filled with tungsten.

Claim 17

The process of claim 12 further including siliciding exposed portions of said polysilicon plugs and polysilicon interconnects to reduce the series resistance thereof in the vertical direction.

Claim 18

The process of claim 15 including strapping at least two of undoped, N + -doped and P + -doped polysilicon areas to form an ohmic interconnect.

Claim 19

A process for forming a self-aligned planarized CMOS transistor using a buried etch stop wherein N-wells and P-wells are formed in a major surface of a semiconductor, and wherein source, gate, drain and interconnect elements are to be formed, comprising: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said semiconductor surface, said multi-layer structure comprising (1) a first layer consisting essentially of a field oxide, (2) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said field oxide, (3) a third layer consisting essentially of an oxide, and (4) a fourth layer consisting essentially of polysilicon or silicon nitride; (c) using a slot mask in conjunction with a resist layer formed on said multi-layer structure to lithographically define a plurality of slots corresponding to various elements of said devices, thereby self-aligning said elements with each other; (d) etching portions of said fourth and third corresponding to said slots, stopping at said etch-stop layer; (e) stripping said resist layer; (f) using an active mask in conjunction with another resist layer formed on said multi-layer structure to define only said active area encompassing a group of said slots associated with an individual device; (g) removing any remaining portions of said etch-stop layer in said slots, along with said field oxide therein; (h) forming a thin oxide on the exposed portions of said semiconductor in said slots associated with said gates of said device; (i) filling said slots with polysilicon to form polysilicon plugs and planarizing to the surface of said multi-layer structure; (j) implanting dopant species into said polysilicon-filled slots associated with said sources and drains of said device; (k) doping at least some of said polysilicon plugs to change the conductivity thereof; (l) applying a connector mask to expose portions of said multi-layer structure between said source and said gate and between said drain and said gate; (m) etching exposed portions of said third layer back to said buried etch-stop layer; (n) etching exposed portions of said etch-stop layer to said field oxide layer; and (o) implanting dopant species through exposed portions of said field oxide layer to form channel regions between said source and said gate and between said drain and said gate and for simultaneously doping the gate polysilicon electrode either n- or p-type.

Claim 20

A process for forming a self-aligned planarized CMOS transistor using a buried etch stop wherein N-wells and P-wells are formed in a major surface of a semiconductor, and wherein source, gate, drain and interconnect elements are to be formed, comprising: (a) delineating an active area within which individual devices are made by forming an oxide region in said substrate therearound; (b) forming a multi-layer structure on said semiconductor surface, said multi-layer structure comprising (1) a first layer consisting essentially of a field oxide, (2) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said field oxide, (3) a third layer consisting essentially of an oxide, and (4) a fourth layer consisting essentially of polysilicon or silicon nitride; (c) using a slot mask in conjunction with a resist layer formed on said multi-layer structure to lithographically define a plurality of slots corresponding to various elements of said devices, thereby self-aligning said elements with each other; (d) etching portions of said fourth and third corresponding to said slots, stopping at said etch-stop layer; (e) stripping said resist layer; (f) using an active mask in conjunction with another resist layer formed on said multi-layer structure to define only said active area encompassing a group of said slots associated with an individual device; (g) removing any remaining portions of said etch-stop layer in said slots, along with said field oxide therein; (h) forming a thin oxide on the exposed portions of said semiconductor in said slots associated with said gates of said device; (i) filling said slots with polysilicon to form polysilicon plugs and planarizing to the surface of said multi-layer structure; (j) implanting dopant species into said polysilicon-filled slots associated with said sources and drains of said device; (k) doping at least some of said polysilicon plugs to change the conductivity thereof; (l) applying a connector mask to expose portions of said multi-layer structure between said source and said gate and between said drain and said gate; (m) etching exposed portions of said third layer back to said buried etch-stop layer; (n) etching exposed portions of said etch-stop layer to said field oxide layer; and (o) implanting dopant species through exposed portions of said field oxide layer to form channel regions between said source and said gate and between said drain and said gate and for simultaneously doping the gate polysilicon electrode either n- or p-type.

Claim 21

The process of claim 17 further including siliciding exposed portions of said polysilicon plugs and polysilicon interconnects to reduce the series resistance thereof in the vertical direction.

Claim 22

The process of claim 18 including strapping at least two of undoped, N + -doped and P + -doped polysilicon areas to form an ohmic interconnect.

Claim 23

The process of claim 17 wherein said semiconductor device includes source, drain and channel regions formed in said semiconductor, said process further including forming lightly-doped source and drain connector regions connecting said source and drain regions, respectively, with said channel region.