Programmable logic array having an improved testing arrangement

Claim 1

A programmable logic array having an AND array, comprising: a plurality of input lines (1a-1c); a plurality of product term lines (30a, 30b); a plurality of non-volatile memory elements (Q 11 -Q 16 , Q 21 -Q 26 ) respectively interposed between said input lines and said product term lines; a test line (1d) for inputting a test signal, and test elements (Q 17 , Q 18 ) respectively interposed between said test line and said product term lines; and control means for, in a test mode for measuring AC characteristics of said programmable logic array, turning OFF those non-volatile memory elements which are connected to said input lines other than said test input line and setting to a low level all product term lines other than said product term line whose AC characteristics are to be measured to a low level, said means selectively applying to said test line a test signal causing said test elements to selectively alternate setting to a high level and a low level the product line whose AC characteristics are to be measured; said programmable logic array including a program circuit (9), a gate transistor Q 0 through which said program circuit is coupled to said product term lines, line selection transistors (Q 1 , Q 2 ) interposed in respective product term lines between the point at which the product term lines are coupled with said program circuit through said gate transistor and the points at which the product term lines are coupled with said non-volatile elements, a decoder (8a) coupled with said line selection transistors to control their OFF/ON states, and a pull-up transistor (Q 3 ) coupled to said product term lines at points thereof which are between said gate transistor and said line selection transistors to selectively set respective lines to a low level.