US6134175A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory address decode array with vertical transistors
Assignee: Micron Technology Inc
•
Filing: 1998-08-04
•
Granted: 2000-10-17
•
Expires: 2018-08-04
Abstract
Abstract A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number of vertical transistors are selectively disposed at intersections of output lines and address lines. Each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate. The vertical transistors each include source, drain, and body regions. A gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines. The transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.
Inventors
- 👤 Leonard Forbes
- 👤 Wendell P. Noble
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:38
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; Y; Y10; Y10S; Y10S257/00; Y10S257/908
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
131 words
A decoder for a memory device, comprising: a number of address lines; a number of output lines; wherein the address lines, and the output lines form an array; and a number of vertical transistors that are selectively disposed at intersections of output lines and address lines, wherein each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistor, a gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines such that the transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.
Claim 2
Dependent Claim
131 words
A decoder for a memory device, comprising: a number of address lines; a number of output lines; wherein the address lines, and the output lines form an array; and a number of vertical transistors that are selectively disposed at intersections of output lines and address lines, wherein each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistor, a gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines such that the transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.
Claim 3
Dependent Claim
42 words
The decoder of claim 1, wherein the number of address lines includes a number of complementary address lines that are disposed in the array with vertical transistors selectively formed in pillars at intersections of the complementary address lines with the output lines.
Claim 4
Dependent Claim
18 words
The decoder of claim 1, wherein address lines are disposed in trenches that separate adjacent rows of pillars.
Claim 5
Dependent Claim
47 words
The decoder of claim 3, wherein the vertical transistors are each formed in one pillar with one of the address lines forming a gate adjacent to a sidewall of the body region of the pillar, and an output line coupled to a drain region of the pillar.
Claim 6
Dependent Claim
14 words
The decoder of claim 4, wherein two address lines are formed in each trench.
Claim 7
Dependent Claim
55 words
The decoder of claim 3, wherein the vertical transistors are each formed in a pair of adjacent pillars with an address line passing between the pillars and forming gates adjacent to a sidewall of the body region of each pillar in the pair, and an output line coupled to a drain region of each pillar.
Claim 8
Dependent Claim
12 words
The decoder of claim 1, wherein the substrate is a bulk semiconductor.
Claim 9
Dependent Claim
23 words
The decoder of claim 1, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.
Claim 10
Dependent Claim
19 words
The decoder of claim 1, wherein the decoder is operatively coupled to a dynamic random access memory (DRAM) device.
Claim 11
Dependent Claim
17 words
The decoder of claim 1, wherein the array includes N address lines and 2 N output lines.
Claim 12
Dependent Claim
55 words
The decoder of claim 1, wherein the number of address lines includes a number of complementary address lines that are each coupled to one of the address lines through an inverter and are disposed in the array with vertical transistors selectively formed in pillars at intersections of the complementary address lines with the output lines.
Claim 13
Dependent Claim
161 words
A memory device, comprising: an array of word lines and complementary bit line pairs; a number of memory cells that are each addressably coupled at intersections of a word line with a bit line of a complementary bit line pair; a row decoder that is coupled to the word lines so as to implement a logic function that selects one of the word lines responsive to an address provided to the row decoder; a number of sense amplifiers, each coupled to a complementary pair of bit lines; a column decoder that is coupled to the sense amplifiers so as to implement a logic function that selects one of the complementary pairs of bit lines responsive to an address provided to the column decoder; and wherein the row decoder comprises an array of vertical transistors that are formed in pillars of semiconductor material and that are selectively coupled to implement a logic function that selects a wordline based on a supplied address.
Claim 14
Dependent Claim
161 words
A memory device, comprising: an array of word lines and complementary bit line pairs; a number of memory cells that are each addressably coupled at intersections of a word line with a bit line of a complementary bit line pair; a row decoder that is coupled to the word lines so as to implement a logic function that selects one of the word lines responsive to an address provided to the row decoder; a number of sense amplifiers, each coupled to a complementary pair of bit lines; a column decoder that is coupled to the sense amplifiers so as to implement a logic function that selects one of the complementary pairs of bit lines responsive to an address provided to the column decoder; and wherein the row decoder comprises an array of vertical transistors that are formed in pillars of semiconductor material and that are selectively coupled to implement a logic function that selects a wordline based on a supplied address.
Claim 15
Dependent Claim
142 words
The memory device of claim 12, wherein the row decoder includes: a number of address lines; a number of output lines that are selectively coupled to the wordlines; wherein the address lines, and the output lines form an array; and a number of vertical transistors that are selectively disposed at intersections of output lines and address lines, wherein each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistor, a gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines such that the transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.
Claim 16
Dependent Claim
43 words
The memory device of claim 13, wherein the number of address lines includes a number of complementary address lines that are disposed in the array with vertical transistors selectively formed in pillars at intersections of the complementary address lines with the output lines.
Claim 17
Dependent Claim
19 words
The memory device of claim 13, wherein address lines are disposed in trenches that separate adjacent rows of pillars.
Claim 18
Dependent Claim
48 words
The memory device of claim 15, wherein the vertical transistors are each formed in one pillar with one of the address lines forming a gate adjacent to a sidewall of the body region of the pillar, and an output line coupled to a drain region of the pillar.
Claim 19
Dependent Claim
15 words
The memory device of claim 16, wherein two address lines are formed in each trench.
Claim 20
Dependent Claim
56 words
The memory device of claim 15, wherein the vertical transistors are each formed in a pair of adjacent pillars with an address line passing between the pillars and forming gates adjacent to a sidewall of the body region of each pillar in the pair, and an output line coupled to a drain region of each pillar.
Claim 21
Dependent Claim
13 words
The memory device of claim 13, wherein the substrate is a bulk semiconductor.
Claim 22
Dependent Claim
24 words
The memory device of claim 13, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.
Claim 23
Dependent Claim
18 words
The memory device of claim 13, wherein the array includes N address lines and 2 N output lines.
Claim 24
Dependent Claim
56 words
The memory device of claim 13, wherein the number of address lines includes a number of complementary address lines that are each coupled to one of the address lines through an inverter and are disposed in the array with vertical transistors selectively formed in pillars at intersections of the complementary address lines with the output lines.
Claim 25
Dependent Claim
181 words
A computer system, comprising: a microprocessor; a memory device coupled to the microprocessor; and wherein the memory device comprises: an array of word lines and complementary bit line pairs; a number of memory cells that are each addressably coupled at intersections of a word line with a bit line of a complementary bit line pair; a row decoder that is coupled to the word lines so as to implement a logic function that selects an one of the word lines responsive to an address provided to the row decoder; a number of sense amplifiers, each coupled to a complementary pair of bit lines; a column decoder that is coupled to the sense amplifiers so as to implement a logic function that selects one of the complementary pairs of bit lines responsive to an address provided to the column decoder; and wherein the row decoder comprises an array of vertical transistors that are formed in pillars of semiconductor material and that are coupled to implement a logic function that selects a wordline or complementary bit line pair based on a supplied address.
Claim 26
Dependent Claim
181 words
A computer system, comprising: a microprocessor; a memory device coupled to the microprocessor; and wherein the memory device comprises: an array of word lines and complementary bit line pairs; a number of memory cells that are each addressably coupled at intersections of a word line with a bit line of a complementary bit line pair; a row decoder that is coupled to the word lines so as to implement a logic function that selects an one of the word lines responsive to an address provided to the row decoder; a number of sense amplifiers, each coupled to a complementary pair of bit lines; a column decoder that is coupled to the sense amplifiers so as to implement a logic function that selects one of the complementary pairs of bit lines responsive to an address provided to the column decoder; and wherein the row decoder comprises an array of vertical transistors that are formed in pillars of semiconductor material and that are coupled to implement a logic function that selects a wordline or complementary bit line pair based on a supplied address.
Claim 27
Dependent Claim
141 words
The system of claim 23, wherein the row decoder includes: a number of address lines; a number of output lines that are selectively coupled to the wordlines; wherein the address lines, and the output lines form an array; and a number of vertical transistors that are selectively disposed at intersections of output lines and address lines, wherein each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain, and body regions for the transistor, a gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines such that the transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.
Claim 28
Dependent Claim
42 words
The system of claim 24, wherein the number of address lines includes a number of complementary address lines that are disposed in the array with vertical transistors selectively formed in pillars at intersections of the complementary address lines with the output lines.
Claim 29
Dependent Claim
18 words
The system of claim 24, wherein address lines are disposed in trenches that separate adjacent rows of pillars.
Claim 30
Dependent Claim
47 words
The system of claim 26, wherein the vertical transistors are each formed in one pillar with one of the address lines forming a gate adjacent to a sidewall of the body region of the pillar, and an output line coupled to a drain region of the pillar.
Claim 31
Dependent Claim
14 words
The system of claim 27, wherein two address lines are formed in each trench.
Claim 32
Dependent Claim
55 words
The system of claim 26, wherein the vertical transistors are each formed in a pair of adjacent pillars with an address line passing between the pillars and forming gates adjacent to a sidewall of the body region of each pillar in the pair, and an output line coupled to a drain region of each pillar.
Claim 33
Dependent Claim
12 words
The system of claim 26, wherein the substrate is a bulk semiconductor.
Claim 34
Dependent Claim
23 words
The system of claim 26, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.
Claim 35
Dependent Claim
17 words
The system of claim 26, wherein the array includes N address lines and 2 N output lines.
Claim 36
Dependent Claim
55 words
The system of claim 26, wherein the number of address lines includes a number of complementary address lines that are each coupled to one of the address lines through an inverter and are disposed in the array with vertical transistors selectively formed in pillars at intersections of the complementary address lines with the output lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-17 | 2004-04-17 | 2004-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-17 | 2008-04-17 | 2008-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-17 | 2012-04-17 | 2012-10-17 | $7700.00 | Window Closed / Lapsed |