US6072209A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Four F2 folded bit line DRAM cell structure having buried bit and word lines
Assignee: Micron Technology Inc
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Filing: 1997-07-08
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Granted: 2000-06-06
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Expires: 2017-07-08
Abstract
Abstract A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transistors of adjacent memory cells, and a pair of word lines are located in each of the isolation trenches. The word lines are oriented vertically widthwise in the trench and are adapted to gate alternate access transistors, so that both an active and a passing word line can be contained within each memory cell to provide a folded bit line architecture. The memory cell has a surface area that is approximately 4 F 2 , where F is a minimum feature size. Also disclosed are processes for fabricating the DRAM cell using bulk silicon or a silicon on insulator processing techniques.
Inventors
- 👤 Wendell P. Noble
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:59
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/053; H10B12/30; H10B12/34
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
173 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; an access transistor fabricated as a vertical structure on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; and a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide on only one side of the vertical structure, and wherein the bit line and the word line are located below the active silicon surface of the memory cell structure.
Claim 2
Dependent Claim
173 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; an access transistor fabricated as a vertical structure on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; and a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide on only one side of the vertical structure, and wherein the bit line and the word line are located below the active silicon surface of the memory cell structure.
Claim 3
Dependent Claim
24 words
The memory cell structure according to claim 1, wherein the word line is oriented vertically widthwise along the sidewall portion of the access transistor.
Claim 4
Dependent Claim
205 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; an access transistor fabricated as a vertical structure on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide, and wherein the bit line and the word line are located below the active silicon surface of the memory cell structure; wherein the word line is oriented vertically widthwise along the sidewall portion of the access transistor; and a layer of a dielectric material interposed between the bit line and the substrate for electrically isolating the bit line, and the access transistor fabricated on the bit line, from the substrate.
Claim 5
Dependent Claim
205 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; an access transistor fabricated as a vertical structure on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide, and wherein the bit line and the word line are located below the active silicon surface of the memory cell structure; wherein the word line is oriented vertically widthwise along the sidewall portion of the access transistor; and a layer of a dielectric material interposed between the bit line and the substrate for electrically isolating the bit line, and the access transistor fabricated on the bit line, from the substrate.
Claim 6
Dependent Claim
200 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; an access transistor fabricated as a vertical structure on on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide, and wherein the bit line and the word line are located below the active silicon surface of the memory cell structure; wherein the word line is oriented vertically widthwise along the sidewall portion of the access transistor; and wherein the surface area of the memory cell structure is approximately 4F 2 , where F is a minimum feature size of the memory cell structure.
Claim 7
Dependent Claim
200 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; an access transistor fabricated as a vertical structure on on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide, and wherein the bit line and the word line are located below the active silicon surface of the memory cell structure; wherein the word line is oriented vertically widthwise along the sidewall portion of the access transistor; and wherein the surface area of the memory cell structure is approximately 4F 2 , where F is a minimum feature size of the memory cell structure.
Claim 8
Dependent Claim
281 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor and being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell.
Claim 9
Dependent Claim
281 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor and being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell.
Claim 10
Dependent Claim
52 words
The memory array according to claim 5, including a second isolation trench extending orthogonally to the first-mentioned isolation trench, the second isolation trench containing a dielectric material for providing isolation between the first and second bit lines, and between the first and third access transistors, and between the second and fourth transistors.
Claim 11
Dependent Claim
45 words
The memory array according to claim 5, wherein the first and second access transistors each are formed as a vertical structure on the first bit line, and the third and fourth access transistors each are formed as a vertical structure on the second bit line.
Claim 12
Dependent Claim
43 words
The memory array according to claim 7, wherein the first bit line functions as the first source/drain region for the first and second access transistors, and the second bit line functions as the first source/drain region for the third and fourth access transistors.
Claim 13
Dependent Claim
103 words
The memory array according to claim 7, including a gate oxide layer formed on a sidewall of the first access transistor and interposed between the first word line and the channel region of the first access transistor, a gate oxide layer formed on a sidewall of the fourth access transistor and interposed between the second word line and the channel region of the fourth access transistor, and a layer of a dielectric material interposed between the channel region of the second access transistor and the first word line and between the channel region of the third access transistor and the second word line.
Claim 14
Dependent Claim
40 words
The memory array according to claim 5, including a layer of a dielectric material interposed between the bit lines and the substrate for electrically isolating the bit lines, and the access transistors formed on the bit lines, from the substrate.
Claim 15
Dependent Claim
238 words
A folded bit line semiconductor memory array fabricated on a semiconductor substrate, the memory array comprising: at least first and second bit lines on the substrate, the first and second bit lines each having a width F which corresponds to a minimum feature size for the semiconductor memory array; at least first and second access transistors formed on each of the bit lines, each of the access transistors being formed as a vertical structure to have first and second source/drain regions and a vertical channel region, the length and the width of each access transistor corresponding to the minimum feature size F; a dielectrically lined trench extending orthogonally to the bit lines between the first and second access transistors on the first and second bit lines; a gate oxide overlying the channel region of the first access transistor on the first and second bit lines; and first and second word lines in each trench, the word lines being oriented vertically widthwise in the trench, the first and second word lines being electrically coupled to the channel region of respective ones of the first access transistors on the first and second bit lines and being electrically isolated from the channel region of respective ones of the second access transistors on the first and second bit lines, providing approximately 0.5 F pitch for the word lines, and wherein the surface area of the memory cell is approximately 4F 2 .
Claim 16
Dependent Claim
238 words
A folded bit line semiconductor memory array fabricated on a semiconductor substrate, the memory array comprising: at least first and second bit lines on the substrate, the first and second bit lines each having a width F which corresponds to a minimum feature size for the semiconductor memory array; at least first and second access transistors formed on each of the bit lines, each of the access transistors being formed as a vertical structure to have first and second source/drain regions and a vertical channel region, the length and the width of each access transistor corresponding to the minimum feature size F; a dielectrically lined trench extending orthogonally to the bit lines between the first and second access transistors on the first and second bit lines; a gate oxide overlying the channel region of the first access transistor on the first and second bit lines; and first and second word lines in each trench, the word lines being oriented vertically widthwise in the trench, the first and second word lines being electrically coupled to the channel region of respective ones of the first access transistors on the first and second bit lines and being electrically isolated from the channel region of respective ones of the second access transistors on the first and second bit lines, providing approximately 0.5 F pitch for the word lines, and wherein the surface area of the memory cell is approximately 4F 2 .
Claim 17
Dependent Claim
290 words
A semiconductor memory device comprising: a memory array fabricated on a semiconductor substrate and including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; memory array access circuitry for accessing the memory cells; each of said memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and an isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor and being electrically isolated from the channel region of the third access transistor, and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being electrically isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, and the first and second word lines being buried in the dielectric material in the isolation trench and located below an active silicon surface of the access transistors.
Claim 18
Dependent Claim
290 words
A semiconductor memory device comprising: a memory array fabricated on a semiconductor substrate and including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; memory array access circuitry for accessing the memory cells; each of said memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and an isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor and being electrically isolated from the channel region of the third access transistor, and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being electrically isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, and the first and second word lines being buried in the dielectric material in the isolation trench and located below an active silicon surface of the access transistors.
Claim 19
Dependent Claim
46 words
The semiconductor memory device according to claim 12, wherein the first and second access transistors each are formed as a vertical structure on the first bit line, and the third and fourth access transistors each are formed as a vertical structure on the second bit line.
Claim 20
Dependent Claim
44 words
The semiconductor memory device according to claim 13, wherein the first bit line functions as the first source/drain region for the first and second access transistors and the second bit line functions as the first source/drain region for the third and fourth access transistors.
Claim 21
Dependent Claim
104 words
The semiconductor memory device according to claim 13, including a gate oxide layer formed on a sidewall of the first access transistor and interposed between the first word line and the channel region of the first access transistor, a gate oxide layer formed on a sidewall of the fourth access transistor and interposed between the second word line and the channel region of the fourth access transistor, and a layer of a dielectric material interposed between the channel region of the second access transistor and the first word line and between the channel region of the third access transistor and the second word line.
Claim 22
Dependent Claim
24 words
The semiconductor memory device according to claim 12, wherein each memory cell includes a stacked capacitor on the upper surface of the access transistor.
Claim 23
Dependent Claim
41 words
The semiconductor memory device according to claim 12, including a layer of a dielectric material interposed between the bit lines and the substrate for electrically isolating the bit lines, and the access transistors formed on the bit lines, from the substrate.
References Cited (Backward Citations)
US4051354A
Cited
US4604162A
Cited
US5208657A
Cited
US4630088A
Cited
US4761768A
Cited
US4766569A
Cited
US4673962A
Cited
US5102817A
Cited
US4663831A
Cited
JPS6366963A
Cited
US5017504A
Cited
US5427972A
Cited
US4949138A
Cited
US5001526A
Cited
US5072269A
Cited
US5057896A
Cited
US4958318A
Cited
US5327380B1
Cited
US5327380A
Cited
US4920065A
Cited
US5021355A
Cited
US5028977A
Cited
US5316962A
Cited
US5006909A
Cited
US5410169A
Cited
US5216266A
Cited
US5276343A
Cited
US5177576A
Cited
US4987089A
Cited
US5223081A
Cited
US5110752A
Cited
US5202278A
Cited
US5376575A
Cited
US5504357A
Cited
US5177028A
Cited
US5156987A
Cited
US5528062A
Cited
US5466625A
Cited
US5320880A
Cited
US5266514A
Cited
US5422499A
Cited
US5391911A
Cited
US5438009A
Cited
US5616934A
Cited
US5519236A
Cited
US5392245A
Cited
US5644540A
Cited
US5445986A
Cited
US5460316A
Cited
US5483094A
Cited
US5393704A
Cited
US5396093A
Cited
US5492853A
Cited
US5574299A
Cited
US5460988A
Cited
US5414287A
Cited
US5495441A
Cited
US5627390A
Cited
US5440158A
Cited
US5483487A
Cited
US5593912A
Cited
US5508542A
Cited
US5646900A
Cited
US5753947A
Cited
US5497017A
Cited
US5508219A
Cited
US5640342A
Cited
US5691230A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-06 | 2003-12-06 | 2004-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-06 | 2007-12-06 | 2008-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-06 | 2011-12-06 | 2012-06-06 | $7700.00 | Window Closed / Lapsed |