Method of forming a floating gate self-aligned to STI on EEPROM

Claim 1

A method of forming a floating gate self-aligned to a shallow trench isolation (STI) comprising the steps of: providing a semiconductor substrate having shallow trench isolation (STI) regions formed therein and active regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming an anti-reflective arc coating (ARC) layer over said first polysilicon layer; partial etching of said ARC layer until portions of under-lying said first polysilicon layer over said STI regions are exposed; partial etching of said exposed portions of said first polysilicon layer until underlying said STI regions are exposed, thus leaving said active regions in said substrate protected by said ARC layer; removing said ARC layer; forming a nitride layer over said substrate; patterning said nitride layer to form floating gate regions self-aligned to said STI regions until portions of said first polysilicon layer over said active regions are exposed; forming a poly-oxide by oxidizing said exposed portions of said first polysilicon layer; removing said nitride layer; etching remaining said first polysilicon layer by using said poly-oxide as a hard-mask; forming an interpoly oxide layer over said substrate, including over said poly-oxide; forming a second polysilicon layer over said interpoly oxide layer; and patterning said second polysilicon layer to form a control gate in completion of said floating gate of said invention.

Claim 2

A method of forming a floating gate self-aligned to a shallow trench isolation (STI) comprising the steps of: providing a semiconductor substrate having shallow trench isolation (STI) regions formed therein and active regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming an anti-reflective arc coating (ARC) layer over said first polysilicon layer; partial etching of said ARC layer until portions of under-lying said first polysilicon layer over said STI regions are exposed; partial etching of said exposed portions of said first polysilicon layer until underlying said STI regions are exposed, thus leaving said active regions in said substrate protected by said ARC layer; removing said ARC layer; forming a nitride layer over said substrate; patterning said nitride layer to form floating gate regions self-aligned to said STI regions until portions of said first polysilicon layer over said active regions are exposed; forming a poly-oxide by oxidizing said exposed portions of said first polysilicon layer; removing said nitride layer; etching remaining said first polysilicon layer by using said poly-oxide as a hard-mask; forming an interpoly oxide layer over said substrate, including over said poly-oxide; forming a second polysilicon layer over said interpoly oxide layer; and patterning said second polysilicon layer to form a control gate in completion of said floating gate of said invention.

Claim 9

A method of forming a floating gate self-aligned to a shallow trench isolation (STI) comprising the steps of: providing a semiconductor substrate having shallow trench isolation (STI) regions formed therein and active regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming a low-viscosity organic layer over said-first polysilicon layer; partial etching of said low-viscosity organic layer until portions of underlying said first polysilicon layer over said STI regions are exposed; partial etching of said exposed portions of said first polysilicon layer until underlying said STI regions are exposed, thus leaving said active regions in said substrate protected by said low-viscosity organic layer; removing said low-viscosity organic layer; forming a nitride layer over said substrate; patterning said nitride layer to form floating gate regions self-aligned to said STI regions until portions of said first polysilicon layer over said active regions are exposed; forming poly-oxide by oxidizing said exposed portions of said first polysilicon layer; removing said nitride layer; etching remaining said first polysilicon layer by using said poly-oxide as a hard-mask; forming an interpoly oxide over said substrate, including over said poly-oxide; forming a second polysilicon layer over said interpoly oxide; and patterning said second polysilicon layer to form a control gate in completion of said floating gate of said invention.

Claim 10

A method of forming a floating gate self-aligned to a shallow trench isolation (STI) comprising the steps of: providing a semiconductor substrate having shallow trench isolation (STI) regions formed therein and active regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming a low-viscosity organic layer over said-first polysilicon layer; partial etching of said low-viscosity organic layer until portions of underlying said first polysilicon layer over said STI regions are exposed; partial etching of said exposed portions of said first polysilicon layer until underlying said STI regions are exposed, thus leaving said active regions in said substrate protected by said low-viscosity organic layer; removing said low-viscosity organic layer; forming a nitride layer over said substrate; patterning said nitride layer to form floating gate regions self-aligned to said STI regions until portions of said first polysilicon layer over said active regions are exposed; forming poly-oxide by oxidizing said exposed portions of said first polysilicon layer; removing said nitride layer; etching remaining said first polysilicon layer by using said poly-oxide as a hard-mask; forming an interpoly oxide over said substrate, including over said poly-oxide; forming a second polysilicon layer over said interpoly oxide; and patterning said second polysilicon layer to form a control gate in completion of said floating gate of said invention.