US6017795A
Expired / Lapsed
US
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Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-05-06
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Granted: 2000-01-25
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Expires: 2018-05-06
Abstract
Abstract A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.
Inventors
- 👤 Chia-Ta Hsieh
- 👤 Jenn Tsao
- 👤 Di-Son Kuo
- 👤 Yai-Fen Lin
- 👤 Hung-Cheng Sung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:52
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
318 words
A method of forming buried source in a memory cell to increase the coupling ratio for improved program speed comprising the steps of: providing a silicon substrate having a plurality of active and field areas defined; forming a pad oxide layer over said substrate; depositing a first layer of nitride over said pad oxide layer; forming a first patterned photoresist mask over said layer of nitride, wherein said patterns correspond to source regions formed in said active areas of said silicon substrate; etching said first layer of nitride and said pad oxide through openings in said patterned photoresist mask; etching further to form a source line trench in said silicon substrate; removing said firs t photoresist mask; performing a partial selective epitaxial growth (SEG) in said trench; forming a source region in said SEG in said trench over said active regions; removing said first layer of nitride and pad oxide layer; forming a sacrificial oxide over said substrate; removing said sacrificial oxide; forming a layer of gate oxide over said substrate; depositing a first layer of polycrystalline silicon (polysilicon) over said substrate; depositing a second layer of nitride over said first layer of polycrystalline silicon; forming a second patterned photoresist mask over said second layer of nitride; etching said second layer of nitride and said gate oxide through openings in said second patterned photoresist mask; performing ion implantation through said openings in said second patterned photoresist mask; removing said second photoresist mask; performing thermal oxidation of said first layer of polysilicon to form polyoxide and define a floating gate of said memory cell; removing said second layer of nitride; etching said first layer of polysilicon using said polyoxide as a hard mask; forming interpoly oxide over said polyoxide; depositing a second layer of polysilicon over said interpoly oxide; and patterning said second layer of polysilicon to form a control gate to complete the forming of said memory cell.
Claim 2
Independent Claim
318 words
A method of forming buried source in a memory cell to increase the coupling ratio for improved program speed comprising the steps of: providing a silicon substrate having a plurality of active and field areas defined; forming a pad oxide layer over said substrate; depositing a first layer of nitride over said pad oxide layer; forming a first patterned photoresist mask over said layer of nitride, wherein said patterns correspond to source regions formed in said active areas of said silicon substrate; etching said first layer of nitride and said pad oxide through openings in said patterned photoresist mask; etching further to form a source line trench in said silicon substrate; removing said firs t photoresist mask; performing a partial selective epitaxial growth (SEG) in said trench; forming a source region in said SEG in said trench over said active regions; removing said first layer of nitride and pad oxide layer; forming a sacrificial oxide over said substrate; removing said sacrificial oxide; forming a layer of gate oxide over said substrate; depositing a first layer of polycrystalline silicon (polysilicon) over said substrate; depositing a second layer of nitride over said first layer of polycrystalline silicon; forming a second patterned photoresist mask over said second layer of nitride; etching said second layer of nitride and said gate oxide through openings in said second patterned photoresist mask; performing ion implantation through said openings in said second patterned photoresist mask; removing said second photoresist mask; performing thermal oxidation of said first layer of polysilicon to form polyoxide and define a floating gate of said memory cell; removing said second layer of nitride; etching said first layer of polysilicon using said polyoxide as a hard mask; forming interpoly oxide over said polyoxide; depositing a second layer of polysilicon over said interpoly oxide; and patterning said second layer of polysilicon to form a control gate to complete the forming of said memory cell.
Claim 3
Dependent Claim
26 words
The method of claim 1, wherein said forming a pad oxide layer is accomplished by thermal growth at a temperature between about 850 to 950° C.
Claim 4
Dependent Claim
20 words
The method of claim 2, wherein said pad oxide layer has a thickness between about 400 to 500 angstroms (Å).
Claim 5
Dependent Claim
61 words
The method of claim 1, wherein said depositing a first layer of nitride is accomplished with LPCVD at a chamber pressure between about 0.25 to 1.0 torr, temperature between about 650° C. to 750° C. by reacting dichlorosilane (SiCl 2 H 2 )with ammonia (NH 3 ) at flow rates between about 80 to 120 standard cubic centimeters per minute (sccm).
Claim 6
Dependent Claim
20 words
The method of claim 4, wherein the thickness of said layer of nitride is between about 750 to 850 Å.
Claim 7
Dependent Claim
19 words
The method of claim 1, wherein said photoresist mask has a thickness between about 1 to 1.2 micrometers (μm).
Claim 8
Dependent Claim
47 words
The method of claim 1, wherein said etching said first layer of nitride and pad oxide is accomplished with etch recipe comprising Ar, CHF 3 , C 4 F 8 at flow rates between about 60 to 120, 20 to 140 and 0 to 20 sccm, respectively.
Claim 9
Dependent Claim
43 words
The method of claim 1, wherein said etching further to form a source trench in said silicon substrates is accomplished with etch recipe comprising O 2 and CF 4 at flow rates between about 50 to 150 and 0 to 20 sccm, respectively.
Claim 10
Dependent Claim
19 words
The method of claim 8, wherein said source trench has a depth between about 700 to 800 angstroms (Å).
Claim 11
Dependent Claim
34 words
The method of claim 1, wherein said performing partial selective epitaxial growth (SEG) in said trench is accomplished by chemical vapor deposition of SiHBr 3 at a temperature between about 500 to 600° C.
Claim 12
Dependent Claim
39 words
The method of claim 1, wherein said forming a source region is accomplished by implanting arsenic ions with a dosage between about 3.0×10 15 to 5.0×10 15 atom/cm 2 and at an energy between about 60 to 90 KeV.
Claim 13
Dependent Claim
48 words
The method of claim 1, wherein said removing said first layer of nitride and pad oxide layer is accomplished with a recipe comprising Ar, CHF 3 , C 4 F 8 at flow rates between about 60 to 120, 20 to 140 and 0 to 20 sccm, respectively.
Claim 14
Dependent Claim
25 words
The method of claim 1, wherein said forming a sacrificial oxide is accomplished by thermal growth at a temperature between about 800 to 900° C.
Claim 15
Dependent Claim
43 words
The method of claim 1, wherein said removing of said sacrificial oxide is accomplished with a recipe comprising Ar, CHF 3 , C 4 F 8 at flow rates between about 60 to 120, 20 to 140 and 0 to 20 sccm, respectively.
Claim 16
Dependent Claim
27 words
The method of claim 1, wherein said forming a layer of gate oxide is accomplished by thermal growth at a temperature between about 850 to 950° C.
Claim 17
Dependent Claim
21 words
The method of claim 15, wherein said layer of gate oxide has a thickness between about 500 to 600 angstroms (Å).
Claim 18
Dependent Claim
31 words
The method of claim 1, wherein said depositing a first layer of polysilicon is accomplished with silicon source SiH 4 using LPCVD at a temperature between about 600 to 650° C.
Claim 19
Dependent Claim
21 words
The method of claim 1, wherein said first layer of polysilicon has a thickness between about 2400 to 2800 angstroms (Å).
Claim 20
Dependent Claim
61 words
The method of claim 1, wherein said depositing a second layer of nitride is accomplished with LPCVD at a chamber pressure between about 0.25 to 1.0 torr, temperature between about 650° C. to 750° C. by reacting dichlorosilane (SiCl 2 H 2 )with ammonia (NH 3 ) at flow rates between about 80 to 120 standard cubic centimeters per minute (sccm).
Claim 21
Dependent Claim
21 words
The method of claim 19, wherein the thickness of said second layer of nitride is between about 750 to 850 Å.
Claim 22
Dependent Claim
20 words
The method of claim 1, wherein said second photoresist mask has a thickness between about 1 to 1.2 micrometers (μm).
Claim 23
Dependent Claim
54 words
The method of claim 1, wherein said etching said second layer of nitride and gate oxide through openings in said second photoresist mask is accomplished with etch recipe comprising Ar, CHF 3 , C 4 F 8 at flow rates between about 60 to 120, 20 to 140 and 0 to 20 sccm, respectively.
Claim 24
Dependent Claim
44 words
The method of claim 1, wherein performing ion implantation through said openings in said second patterned photoresist mask is accomplished using phosphorus at a dosage level between about 5×10 6 to 7×10 6 atoms/cm 2 with energy level between about 40 to 60 KeV.
Claim 25
Dependent Claim
33 words
The method of claim 1, wherein said performing thermal oxidation of said first layer of polysilicon to form polyoxide is accomplished by wet oxidation at a temperature between about 860 to 910° C.
Claim 26
Dependent Claim
44 words
The method of claim 1, wherein said removing said second layer of nitride is accomplished with a recipe comprising Ar, CHF 3 , C 4 F 8 at flow rates between about 60 to 120, 20 to 140 and 0 to 20 sccm, respectively.
Claim 27
Dependent Claim
36 words
The method of claim 1, wherein said etching said first layer of polysilicon using said polyoxide as a hard mask is accomplished with a recipe comprising gases HBr, CL 2 , He and O 2 .
Claim 28
Dependent Claim
20 words
The method of claim 1, wherein said interpoly oxide is oxynitride with a thickness between about 350 to 400 Å.
Claim 29
Dependent Claim
35 words
The method of claim 1, wherein said depositing a second layer of polysilicon over said interpoly oxide is accomplished with silicon source SiH 4 using LPCVD at a temperature between about 600 to 650° C.
Claim 30
Dependent Claim
25 words
The method of claim 28, wherein said second layer of polysilicon to form a control gate has a thickness between about 2600 to 3000 Å.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-01-24 | 2003-07-26 | 2004-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-24 | 2007-07-26 | 2008-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-24 | 2011-07-26 | 2012-01-25 | $7700.00 | Window Closed / Lapsed |