US5395779A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of manufacture of split gate EPROM device
Assignee: United Microelectronics Corp
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Filing: 1994-04-08
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Granted: 1995-03-07
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Expires: 2014-04-08
Abstract
Abstract Fabrication of a MOSFET comprises, forming a dielectric layer on a substrate and a sacrificial structure on portions of the dielectric layer, forming a first polysilicon layer over the sacrificial structure and other exposed surfaces of the device, patterning the first polysilicon layer and the dielectric layer by masking and etching to form a stepped electrode structure partially upon the sacrificial structure and partially upon the other exposed surfaces of the device, applying ion implantation into the substrate outside of the area covered by the stepped electrode structure, removing the sacrificial layer from the surface of the substrate and from beneath the stepped electrode structure leaving an overhanging surface of the stepped electrode structure, forming a second layer of dielectric material on the exposed surfaces of the stepped electrode structure and the substrate, and forming a second polysilicon layer over and under overhanging portions the second layer of dielectric material and the substrate.
Inventors
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10B; H10B69/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
163 words
A method of fabricating a EPROM device on a semiconductor substrate comprising: forming a dielectric layer on said substrate, forming a sacrificial structure on portions of said dielectric layer, forming a first polysilicon layer over said sacrificial structure and other surfaces of said device, patterning said first polysilicon layer and said dielectric layer by masking and etching to form a stepped electrode structure partially upon said sacrificial structure and partially upon said other surfaces of said device, ion implanting into said substrate outside of an area covered by said stepped electrode structure, removing said sacrificial layer from the surface of said substrate and from beneath said stepped electrode structure leaving an overhanging surface of said stepped electrode structure, forming a second layer of dielectric material on exposed surfaces of said stepped electrode structure and said substrate, and forming a second polysilicon layer over and under overhanging portions of said stepped electrode structure and over said second layer of dielectric material and said substrate.
Claim 2
Independent Claim
163 words
A method of fabricating a EPROM device on a semiconductor substrate comprising: forming a dielectric layer on said substrate, forming a sacrificial structure on portions of said dielectric layer, forming a first polysilicon layer over said sacrificial structure and other surfaces of said device, patterning said first polysilicon layer and said dielectric layer by masking and etching to form a stepped electrode structure partially upon said sacrificial structure and partially upon said other surfaces of said device, ion implanting into said substrate outside of an area covered by said stepped electrode structure, removing said sacrificial layer from the surface of said substrate and from beneath said stepped electrode structure leaving an overhanging surface of said stepped electrode structure, forming a second layer of dielectric material on exposed surfaces of said stepped electrode structure and said substrate, and forming a second polysilicon layer over and under overhanging portions of said stepped electrode structure and over said second layer of dielectric material and said substrate.
Claim 3
Dependent Claim
18 words
A method in accordance with claim 1 wherein said ion implanting into said substrate forms buried bit lines.
Claim 4
Dependent Claim
45 words
A method in accordance with claim 2 wherein said buried bit lines are implanted into said substrate with N+ dopant with an energy of between about 30 to 100 kev, and a dose of between about 1 E 15 to 6 E 16/cm 2 .
Claim 5
Dependent Claim
37 words
A method in accordance with claim 1 wherein after implanting said buried bit lines into said substrate a step of forming a self aligned oxide structure is performed by oxidation of the exposed surface of said substrate.
Claim 6
Dependent Claim
31 words
A method in accordance with claim 4 wherein said self aligned oxide structure is formed by oxidation in oxygen gas (O 2 ) at a temperature of about 900 ° C.
Claim 7
Dependent Claim
22 words
A method in accordance with claim 5 wherein said oxidation continues until a thickness of about 300 to 1500 Å is obtained.
Claim 8
Dependent Claim
21 words
A method in accordance with claim 5 wherein said self aligned thick oxide structure is formed over said buried bit lines.
Claim 9
Dependent Claim
16 words
A method in accordance with claim 5 wherein said second layer of dielectric material comprises ONO.
Claim 10
Independent Claim
203 words
A method of fabricating a EPROM device on a semiconductor substrate comprising: forming a silicon dioxide gate dielectric layer on said substrate, forming a silicon nitride sacrificial structure on portions of said dielectric layer, etching away exposed portions of said gate dielectric layer to expose portions of the surface of said substrate and forming a tunnel oxide layer over exposed surfaces of said substrate, forming a first polysilicon layer over said sacrificial structure and said tunnel oxide layer, patterning said first polysilicon layer and said dielectric layer by masking and etching to form a stepped electrode structure partially upon said sacrificial structure and partially upon said tunnel oxide layer, ion implanting ions into said substrate outside of the area covered by said stepped electrode structure forming buried bit lines in said substrate, removing said sacrificial layer from the surface of said substrate and from beneath said stepped electrode structure leaving an overhanging surface of said stepped electrode structure, forming a second layer of dielectric material on exposed surfaces of said stepped electrode structure and said substrate, and forming a second polysilicon layer over and under overhanging portions of said stepped electrode structure and over said second layer of dielectric material and said substrate.
Claim 11
Independent Claim
203 words
A method of fabricating a EPROM device on a semiconductor substrate comprising: forming a silicon dioxide gate dielectric layer on said substrate, forming a silicon nitride sacrificial structure on portions of said dielectric layer, etching away exposed portions of said gate dielectric layer to expose portions of the surface of said substrate and forming a tunnel oxide layer over exposed surfaces of said substrate, forming a first polysilicon layer over said sacrificial structure and said tunnel oxide layer, patterning said first polysilicon layer and said dielectric layer by masking and etching to form a stepped electrode structure partially upon said sacrificial structure and partially upon said tunnel oxide layer, ion implanting ions into said substrate outside of the area covered by said stepped electrode structure forming buried bit lines in said substrate, removing said sacrificial layer from the surface of said substrate and from beneath said stepped electrode structure leaving an overhanging surface of said stepped electrode structure, forming a second layer of dielectric material on exposed surfaces of said stepped electrode structure and said substrate, and forming a second polysilicon layer over and under overhanging portions of said stepped electrode structure and over said second layer of dielectric material and said substrate.
Claim 12
Dependent Claim
45 words
A method in accordance with claim 9 wherein said buried bit lines are implanted into said substrate with N+ dopant with an energy of between about 30 to 100 kev, and a dose of between about 1 E 15 to 6 E 16/cm 2 .
Claim 13
Dependent Claim
37 words
A method in accordance with claim 9 wherein after implanting said buried bit lines into said substrate a step of forming a self aligned oxide structure is performed by oxidation of the exposed surface of said substrate.
Claim 14
Dependent Claim
30 words
A method in accordance with claim 11 wherein said self aligned oxide structure is formed by oxidation in oxygen gas (O 2 ) at a temperature of about 900° C.
Claim 15
Dependent Claim
22 words
A method in accordance with claim 12 wherein said oxidation continues until a thickness of about 300 to 1500 Å is obtained.
Claim 16
Dependent Claim
20 words
A method in accordance with claim 12 wherein said self aligned oxide structure is formed over said buried bit lines.
Claim 17
Dependent Claim
16 words
A method in accordance with claim 12 wherein said second layer of dielectric material comprises ONO.
References Cited (Backward Citations)
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