US6046086A
Expired / Lapsed
US
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Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-06-19
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Granted: 2000-04-04
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Expires: 2018-06-19
Abstract
Abstract A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split-gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the floating gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.
Inventors
- 👤 Yai-Fen Lin
- 👤 Chia-Ta Hsieh
- 👤 Hung-Cheng Sung
- 👤 Chuang-Ke Yeh
- 👤 Di-Son Kuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:47
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
283 words
A method of forming split-gate flash memories with improved data retention capacity and increased coupling ratio comprising the steps of: providing a silicon substrate having a plurality of active and field areas defined; forming a first gate oxide layer over said substrate; depositing a first nitride layer over said gate oxide layer; forming a first photoresist layer over said first layer of nitride; patterning said first photoresist layer to define a cell area and source size; etching to pattern said first nitride layer and said gate oxide layer correspondingly to a cell area; removing said first photoresist layer from said substrate; forming a second gate oxide layer adjacent to said patterned oxide and nitride layers over cell areas on said substrate; forming a first polysilicon layer over said substrate; forming a second nitride layer over said first polysilicon layer; forming a second photoresist layer over said second nitride layer; patterning said second photoresist layer to define a floating gate region on said substrate; etching said second nitride layer through said patterning in said second photoresist layer and forming openings reaching said first polysilicon layer; performing ion implantation through openings in said second patterned photoresist layer to form source/drain regions within said substrate; removing said second photoresist layer; performing thermal oxidation of said first polysilicon layer exposed in said openings reaching said first polysilicon layer to form regions of poly-oxide; removing said second nitride layer; etching said first polysilicon layer using said regions of poly-oxide as a mask; growing inter-poly oxide over said first polysilicon layer; forming a second polysilicon layer over said inter-poly oxide; and patterning said second polysilicon layer to form a control gate to complete the forming of said memory cell.
Claim 2
Independent Claim
283 words
A method of forming split-gate flash memories with improved data retention capacity and increased coupling ratio comprising the steps of: providing a silicon substrate having a plurality of active and field areas defined; forming a first gate oxide layer over said substrate; depositing a first nitride layer over said gate oxide layer; forming a first photoresist layer over said first layer of nitride; patterning said first photoresist layer to define a cell area and source size; etching to pattern said first nitride layer and said gate oxide layer correspondingly to a cell area; removing said first photoresist layer from said substrate; forming a second gate oxide layer adjacent to said patterned oxide and nitride layers over cell areas on said substrate; forming a first polysilicon layer over said substrate; forming a second nitride layer over said first polysilicon layer; forming a second photoresist layer over said second nitride layer; patterning said second photoresist layer to define a floating gate region on said substrate; etching said second nitride layer through said patterning in said second photoresist layer and forming openings reaching said first polysilicon layer; performing ion implantation through openings in said second patterned photoresist layer to form source/drain regions within said substrate; removing said second photoresist layer; performing thermal oxidation of said first polysilicon layer exposed in said openings reaching said first polysilicon layer to form regions of poly-oxide; removing said second nitride layer; etching said first polysilicon layer using said regions of poly-oxide as a mask; growing inter-poly oxide over said first polysilicon layer; forming a second polysilicon layer over said inter-poly oxide; and patterning said second polysilicon layer to form a control gate to complete the forming of said memory cell.
Claim 3
Dependent Claim
27 words
The method of claim 1, wherein said forming a first gate oxide layer is accomplished by thermal growth at a temperature between about 850 to 950° C.
Claim 4
Dependent Claim
21 words
The method of claim 2, wherein said first gate oxide layer has a thickness between about 50 to 55 angstroms (Å).
Claim 5
Dependent Claim
37 words
The method of claim 1, wherein said depositing a first nitride layer is accomplished by CVD at a temperature between about 750 to 850° C. by reacting dichlorosilane (SiCl 2 H 2 )with ammonia (NH 3 ).
Claim 6
Dependent Claim
20 words
The method of claim 4, wherein the thickness of said first nitride layer is between about 50 to 60 Å.
Claim 7
Dependent Claim
21 words
The method of claim 1, wherein said second patterned photoresist layer has a thickness between about 1 to 1.2 micrometers (μm).
Claim 8
Dependent Claim
33 words
The method of claim 1, wherein said etching said first nitride layer and first gate oxide layer is accomplished with etch recipe comprising gases Ar, CHF 3 , C 4 F 8 .
Claim 9
Dependent Claim
18 words
The method of claim 1, wherein said removing said first photoresist layer is accomplished by oxygen plasma ashing.
Claim 10
Dependent Claim
27 words
The method of claim 1, wherein said forming a second gate oxide layer is accomplished by thermal growth at a temperature between about 850 to 950° C.
Claim 11
Dependent Claim
21 words
The method of claim 9, wherein said second gate oxide layer has a thickness between about 80 to 85 angstroms (Å).
Claim 12
Dependent Claim
30 words
The method of claim 1, wherein said forming a first polysilicon layer is accomplished with silicon source SiH 4 using LPCVD at a temperature between about 550 to 620° C.
Claim 13
Dependent Claim
20 words
The method of claim 11, wherein said first polysilicon layer has a thickness between about 1100 to 1200 angstroms (Å).
Claim 14
Dependent Claim
37 words
The method of claim 1, wherein said forming a second nitride layer is accomplished with LPCVD at a temperature between about 750 to 850° C. by reacting dichlorosilane (SiCl 2 H 2 )with ammonia (NH 3 ).
Claim 15
Dependent Claim
21 words
The method of claim 13, wherein the thickness of said second layer of nitride is between about 750 to 850 Å.
Claim 16
Dependent Claim
20 words
The method of claim 1, wherein said second photoresist layer has a thickness between about 1 to 1.2 micrometers (μm).
Claim 17
Dependent Claim
36 words
The method of claim 1, wherein said etching said second nitride layer through pattern openings in said second photoresist layer is accomplished with etch recipe comprising gases Ar, CHF 3 , C 4 F 8 .
Claim 18
Dependent Claim
41 words
The method of claim 1, wherein said performing thermal oxidation of said first polysilicon layer to form poly-oxide with a thickness between about 1400 to 1500 Å is accomplished by wet oxidation at a temperature between about 850 to 950° C.
Claim 19
Dependent Claim
24 words
The method of claim 1, wherein said removing said second nitride layer is accomplished with a wet solution comprising H 3 PO 4 .
Claim 20
Dependent Claim
34 words
The method of claim 1, wherein said etching said first polysilicon layer using said poly-oxide as a mask is accomplished with a recipe comprising gases HBr, Cl 2 , He and O 2 .
Claim 21
Dependent Claim
18 words
The method of claim 1, wherein said inter-poly oxide has a thickness between about 200 to 300 Å.
Claim 22
Dependent Claim
34 words
The method of claim 1, wherein said forming a second polysilicon layer over said inter-poly oxide is accomplished with silicon source SiH 4 using LPCVD at a temperature between about 550 to 620° C.
Claim 23
Dependent Claim
24 words
The method of claim 21, wherein said second polysilicon layer to form a control gate has a thickness between about 1500 to 2500 Å.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-04-04 | 2003-10-04 | 2004-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-04 | 2007-10-04 | 2008-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-04 | 2011-10-04 | 2012-04-04 | $7700.00 | Window Closed / Lapsed |