US5716865A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making split gate flash EEPROM cell by separating the tunneling region from the channel
Assignee: SK Hynix Inc
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Filing: 1996-03-13
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Granted: 1998-02-10
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Expires: 2016-03-13
Abstract
Abstract The flash EEPROM cell of split-gate type according to the present invention can prevent the degradation of the tunnel oxide film of the cell due to the band-to-band tunneling and the secondary hot carrier which are generated by a high electric field formed at the overlap region between the junction region and the gate electrode when programming and erasure operations are performed by a high voltage to the structure in which the tunneling region is separated from the channel with a thick insulation film.
Inventors
- 👤 Byung Jin Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:55
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/6891; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
300 words
A method manufacturing a flash EEPROM cell, comprising the steps of: forming a buried drain region in a portion of a silicon substrate; forming a first and a second field oxide layers, wherein said second field oxide layer is formed in said silicon substrate in said buried drain region and said first field oxide layer is formed in a portion of said silicon substrate spaced from said second field oxide layer at a distance; forming a gate oxide layer on said silicon substrate between said first and second field oxide layers; sequentially forming a first polysilicon layer and an interpoly insulating layer on the resulting structure after forming said gate oxide layer; sequentially patterning said interpoly insulating layer, said first polysilicon layer and said gate oxide layer, thereby forming a control gate; forming a drain region in said silicon substrate between said control gate and said second field oxide layer so that said drain region is connected to said buried drain region; forming a floating gate oxide layer on the resulting structure after forming said drain region, wherein said floating gate oxide layer on said drain region is formed with thicker than said floating gate oxide layer on the other regions; etching a portion of said floating gate oxide layer which is formed on said drain region and on second field oxide layer to be exposed a portion where said drain region is overlapped to said second field oxide layer; removing said floating gate oxide layer in said silicon substrate between said first field oxide layer and said control gate; sequentially forming a tunnel oxide layer and a second polysilicon layer; forming a floating gate by patterning said second polysilicon layer; and forming a source region in said silicon substrate between said first field oxide layer and said control gate.
Claim 2
Independent Claim
300 words
A method manufacturing a flash EEPROM cell, comprising the steps of: forming a buried drain region in a portion of a silicon substrate; forming a first and a second field oxide layers, wherein said second field oxide layer is formed in said silicon substrate in said buried drain region and said first field oxide layer is formed in a portion of said silicon substrate spaced from said second field oxide layer at a distance; forming a gate oxide layer on said silicon substrate between said first and second field oxide layers; sequentially forming a first polysilicon layer and an interpoly insulating layer on the resulting structure after forming said gate oxide layer; sequentially patterning said interpoly insulating layer, said first polysilicon layer and said gate oxide layer, thereby forming a control gate; forming a drain region in said silicon substrate between said control gate and said second field oxide layer so that said drain region is connected to said buried drain region; forming a floating gate oxide layer on the resulting structure after forming said drain region, wherein said floating gate oxide layer on said drain region is formed with thicker than said floating gate oxide layer on the other regions; etching a portion of said floating gate oxide layer which is formed on said drain region and on second field oxide layer to be exposed a portion where said drain region is overlapped to said second field oxide layer; removing said floating gate oxide layer in said silicon substrate between said first field oxide layer and said control gate; sequentially forming a tunnel oxide layer and a second polysilicon layer; forming a floating gate by patterning said second polysilicon layer; and forming a source region in said silicon substrate between said first field oxide layer and said control gate.
Claim 3
Dependent Claim
28 words
The method of claim 1, wherein said first and second field oxide layers are formed of thickness of 2,000 through 5,000 Å by means of the LOCOS process.
Claim 4
Dependent Claim
19 words
The method of claim 1, wherein said gate oxide layer is formed of thickness of 300 through 500 Å.
Claim 5
Dependent Claim
23 words
The method of claim 1, wherein said interpoly insulating layer is formed of double structure having an oxide layer and a nitride layer.
Claim 6
Dependent Claim
18 words
The method of claim 1, wherein said floating gate oxide layer is formed by a wet oxidization process.
Claim 7
Dependent Claim
19 words
The method of claim 1, wherein said tunnel oxide layer is formed of thickness of 80 through 120 Å.
References Cited (Backward Citations)
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