Method for manufacturing an EEPROM cell

Claim 1

A method for manufacturing a full-feature EEPROM cell with a selective-gate transistor and a stacked-gate transistor formed on a first conductivity type of a substrate, said method comprising the steps of: forming a gate isolating layer and a first conductive layer on a region of the substrate to be a selective gate of the selective-gate transistor, and thereby defining a channel region of the selective-gate transistor; forming a masking layer on the selective gate and the substrate; forming an oxide layer over the masking layer and then etching back the oxide layer to form sidewall spacers beside the selective gate and on the masking layer, and defining a channel region of the stacked-gate transistor underlying one of the sidewall spacers; removing the masking layer between the selective gate and the sidewall spacers; doping a second conductivity type of dopant into the first conductivity type of substrate to form lightly doped regions beside the channel regions of the selective-gate transistor and the stacked-gate transistor by using the selective gate and the sidewall spacers as masks; removing the sidewall spacers and the masking layer; forming an insulating layer covering the selective gate and forming a tunnel dielectric layer on the substrate; forming a second conductive layer, a dielectric layer and a third conductive layer on the selective gate and the channel region of the stacked-gate transistor to serve as a stacked gate of the stacked-gate transistor; and implanting a second conductivity type of dopant into the substrate to form heavily doped regions by using the selective gate which is covered with said insulating layer and the stacked gate as masks, so that each of the lightly doped regions, which combine with one of the heavily doped regions to form a LDD structure, respectively forms sources and drains of the selective-gate transistor and the stacked-gate transistor.

Claim 2

A method for manufacturing a full-feature EEPROM cell with a selective-gate transistor and a stacked-gate transistor formed on a first conductivity type of a substrate, said method comprising the steps of: forming a gate isolating layer and a first conductive layer on a region of the substrate to be a selective gate of the selective-gate transistor, and thereby defining a channel region of the selective-gate transistor; forming a masking layer on the selective gate and the substrate; forming an oxide layer over the masking layer and then etching back the oxide layer to form sidewall spacers beside the selective gate and on the masking layer, and defining a channel region of the stacked-gate transistor underlying one of the sidewall spacers; removing the masking layer between the selective gate and the sidewall spacers; doping a second conductivity type of dopant into the first conductivity type of substrate to form lightly doped regions beside the channel regions of the selective-gate transistor and the stacked-gate transistor by using the selective gate and the sidewall spacers as masks; removing the sidewall spacers and the masking layer; forming an insulating layer covering the selective gate and forming a tunnel dielectric layer on the substrate; forming a second conductive layer, a dielectric layer and a third conductive layer on the selective gate and the channel region of the stacked-gate transistor to serve as a stacked gate of the stacked-gate transistor; and implanting a second conductivity type of dopant into the substrate to form heavily doped regions by using the selective gate which is covered with said insulating layer and the stacked gate as masks, so that each of the lightly doped regions, which combine with one of the heavily doped regions to form a LDD structure, respectively forms sources and drains of the selective-gate transistor and the stacked-gate transistor.