Stepped floating gate EPROM device

Claim 2

A MOSFET device formed on a semiconductor substrate comprising: a dielectric layer on said substrate; a first polysilicon layer formed over said dielectric layer in a stepped pattern partially on said dielectric layer and partially a step above said dielectric layer, said first polysilicon layer patterned to form a stepped electrode structure having an overhanging surface; ion implanted regions comprising source/drain for said MOSFET device formed in said substrate outside of the area covered by said stepped electrode structure; a second layer of dielectric material on exposed surfaces of said stepped electrode structure and said substrate; and a second polysilicon layer over and under overhanging portions of said second layer of dielectric material and said stepped electrode structure and said substrate, said stepped electrode structure and said second polysilicon layer separated by said second layer of dielectric material.

Claim 3

A device in accordance with claim 1 with buried bit lines implanted into said substrate, said buried bit lines formed continuous with said source/drain regions.

Claim 4

A device in accordance with claim 2 wherein said buried bit lines have been implanted into said substrate with arsenic (As) N+ dopant with an energy of between about 30 keV and about 100 keV, and a dose of As of between about 1 E 15/cm 2 and 6 E 16/cm 2 .

Claim 5

A device in accordance with claim 1 wherein oxide structures are formed over said source/drain regions, said oxide structures each having an edge self-aligned to said first polysilicon layer.

Claim 6

A device in accordance with claim 4 wherein said oxide structures each have a second edge self aligned to an edge of a floating gate of an adjacent MOSFET device.

Claim 7

A MOSFET device formed on a semiconductor substrate comprising; a first dielectric layer on said substrate; a first polysilicon layer formed over said first dielectric layer, said first polysilicon layer formed in a stepped electrode pattern with a stepped portion spaced above said first dielectric layer and separated from said dielectric layer; a blanket interpolysilicon layer formed over said first polysilicon layer and under said stepped portion of said first polysilicon layer where said first polysilicon layer is spaced above and separated from said first dielectric layer and over exposed portions of said first dielectric layer; a second polysilicon layer formed over said interpolysilicon layer above said first polysilicon layer and under the exposed surfaces of said interpolysilicon layer beneath said stepped portion of said first polysilicon layer whereby said stepped electrode structure has an overhanging surface extending over a portion of a second polysilicon layer with said interpolysilicon layer therebetween; and first and second doped source/drain regions formed along a first and a second edge of said first polysilicon layer, a boundary of said first doped source/drain region formed self aligned to said first edge of said first polysilicon layer.

Claim 8

A MOSFET device formed on a semiconductor substrate comprising; a first dielectric layer on said substrate; a first polysilicon layer formed over said first dielectric layer, said first polysilicon layer formed in a stepped electrode pattern with a stepped portion spaced above said first dielectric layer and separated from said dielectric layer; a blanket interpolysilicon layer formed over said first polysilicon layer and under said stepped portion of said first polysilicon layer where said first polysilicon layer is spaced above and separated from said first dielectric layer and over exposed portions of said first dielectric layer; a second polysilicon layer formed over said interpolysilicon layer above said first polysilicon layer and under the exposed surfaces of said interpolysilicon layer beneath said stepped portion of said first polysilicon layer whereby said stepped electrode structure has an overhanging surface extending over a portion of a second polysilicon layer with said interpolysilicon layer therebetween; and first and second doped source/drain regions formed along a first and a second edge of said first polysilicon layer, a boundary of said first doped source/drain region formed self aligned to said first edge of said first polysilicon layer.

Claim 9

A MOSFET device in accordance with claim 6 wherein a boundary of said second doped source/drain region is formed self aligned to said second edge of said first polysilicon layer.

Claim 10

A MOSFET device in accordance with claim 6 with said doped source/drain regions are formed by ion implantation into said substrate with arsenic (As) N+ dopant with a dose of As between about 1 E 15/Cm 2 and 6 E 16/cm 2 .

Claim 11

A MOSFET device in accordance with claim 6 with a self aligned oxide structure formed self-aligned to said source/drain regions.

Claim 12

A MOSFET device in accordance with claim 9 wherein said doped source/drain regions each have a second boundary self aligned to an edge of a floating gate of an adjacent MOSFET device.

Claim 13

A MOSFET device in accordance with claim 6, where Vg is the voltage on control gate and the device operates in accordance with this TABLE as follows: Division of 08/244,695 filed Apr. 8, 1994 ______________________________________ V.sub.DRAIN V.sub.SOURCE Vg ______________________________________ PROGRAM 6.0 V 0 V 12 V ERASE 12.0 V 0 V 0 V READ 1.5 V 0 V 3 V ______________________________________

Claim 14

A MOSFET device in accordance with claim 6, wherein said second polysilicon layer forms a control gate and a word line as well as the control gate of an isolation transistor T I .

Claim 15

A MOSFET device formed on a semiconductor substrate comprising: a first dielectric layer on said substrate with tunnel oxide regions formed therein; a first polysilicon layer and a second polysilicon layer, said first polysilicon layer formed over said dielectric layer, and said second polysilicon layer formed over said tunnel oxide regions and other exposed surfaces of said device, said first polysilicon layer and said dielectric layer patterned into a stepped electrode structure partially over an interpolysilicon layer and said second polysilicon layer and partially upon said other exposed surfaces of said device, said stepped electrode structure having an overhanging surface extending over a portion of said second polysilicon layer; first and second doped source/drain regions formed along a first and a second edge of said first polysilicon layer, a boundary of said first doped source/drain region formed self aligned to said first edge of said first polysilicon layer and a boundary of said second doped source/drain region formed self aligned to said second edge of said first polysilicon layer; and a second layer of dielectric material on upper surfaces of said stepped electrode structure and said substrate, said second polysilicon layer extending over the top surface of said second layer of dielectric material and under overhanging portions of said second laver of said dielectric material and said substrate.

Claim 16

A MOSFET device formed on a semiconductor substrate comprising: a first dielectric layer on said substrate with tunnel oxide regions formed therein; a first polysilicon layer and a second polysilicon layer, said first polysilicon layer formed over said dielectric layer, and said second polysilicon layer formed over said tunnel oxide regions and other exposed surfaces of said device, said first polysilicon layer and said dielectric layer patterned into a stepped electrode structure partially over an interpolysilicon layer and said second polysilicon layer and partially upon said other exposed surfaces of said device, said stepped electrode structure having an overhanging surface extending over a portion of said second polysilicon layer; first and second doped source/drain regions formed along a first and a second edge of said first polysilicon layer, a boundary of said first doped source/drain region formed self aligned to said first edge of said first polysilicon layer and a boundary of said second doped source/drain region formed self aligned to said second edge of said first polysilicon layer; and a second layer of dielectric material on upper surfaces of said stepped electrode structure and said substrate, said second polysilicon layer extending over the top surface of said second layer of dielectric material and under overhanging portions of said second laver of said dielectric material and said substrate.

Claim 17

A MOSFET device in accordance with claim 1, wherein said stepped electrode pattern of said first polysilicon layer is surrounded by said second polysilicon layer, and said second polysilicon layer comprises a control gate and said stepped electrode structure comprising a floating gate.

Claim 18

A MOSFET device in accordance with claim 6, wherein said stepped electrode structure of said first polysilicon layer is surrounded by said second polysilicon layer, and said second polysilicon layer comprises a control gate and said stepped electrode structure comprising a floating gate.

Claim 19

A MOSFET device in accordance with claim 13, wherein said stepped electrode structure of said first polysilicon layer is surrounded by said second Division of 08/224,695 filed Apr. 8, 1994 polysilicon layer is surrounded by said second polysilicon layer, said second polysilicon layer comprises a control gate and said stepped electrode structure comprising a floating gate.

Claim 20

A MOSFET device in accordance with claim 13 with buried bit lines implanted into said substrate, the first and second source/drain regions forming part of a pair of said buried bit lines.

Claim 21

A MOSFET device in accordance with claim 17 with said buried bit lines having been implanted into said substrate with arsenic (As) N+ dopant with a dose of As between about 1 E 15/cm 2 and 6 E 16/cm 2 .

Claim 22

A MOSFET device in accordance with claim 13 with a self aligned oxide structure formed self-aligned to said buried bit lines.

Claim 23

A MOSFET device in accordance with claim 13, where Vg is the voltage on control gate and the device operates in accordance with this TABLE as follows: ______________________________________ V.sub.DRAIN V.sub.SOURCE Vg ______________________________________ PROGRAM 6.0 V 0 V 12 V ERASE 12.0 V 0 V 0 V READ 1.5 V 0 V 3 V ______________________________________ .