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US6037266A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher

Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-09-28
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Granted: 2000-03-14
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Expires: 2018-09-28
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Abstract

Abstract A method of patterning a polysilicon gate using an oxide hard mask using a novel 4 step insitu etch process. All 4 etch steps are performed insitu in a polysilicon high density plasma (TCP-transformer coupled plasma) etcher. A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30. The 4 step insitu etch process comprises: a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer by flowing HBr and O2 gasses, and applying a first TCP Power and a first Bias power; b) in STEP 2, etching the hard mask by flowing a flouorocarbon gas; and applying a second TCP Power and second Bias power; c) in STEP 3-stripping the bottom anti-reflective coating (BARC) layer by flowing oxygen and applying a third TCP Power and a third Bias power; d) in STEP 4-etching the polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a fourth TCP Power and a fourth Bias power.

Inventors

  • 👤 Hun-Jan Tao
  • 👤 Chia-Shiung Tsai

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 10:14
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 180 words
A method of fabricating a submicron polysilicon gate; comprising the steps of: forming sequentially a gate oxide layer, a polysilicon layer, a hard mask layer composed of silicon oxide, and a bottom anti-reflective coating (BARC) layer over a substrate; forming a resist layer over said bottom anti-reflective coating (BARC) layer; said resist layer defining said polysilicon gate; placing said substrate into a polysilicon high density plasma etcher and performing the following steps: a) in STEP 1, etching said bottom anti-reflective coating (BARC) layer by flowing bromine species gas and oxygen species gas, and applying a first TCP Power and a first Bias power; b) in STEP 2, etching said hard mask by flowing a flouorocarbon gas; and applying a second TCP Power and second Bias power; c) in STEP 3--stripping said bottom anti-reflective coating (BARC) layer by flowing oxygen and applying a third TCP Power and a third Bias power; d) in STEP 4--etching said polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a fourth TCP Power and a fourth Bias power.
Claim 2
Independent Claim 180 words
A method of fabricating a submicron polysilicon gate; comprising the steps of: forming sequentially a gate oxide layer, a polysilicon layer, a hard mask layer composed of silicon oxide, and a bottom anti-reflective coating (BARC) layer over a substrate; forming a resist layer over said bottom anti-reflective coating (BARC) layer; said resist layer defining said polysilicon gate; placing said substrate into a polysilicon high density plasma etcher and performing the following steps: a) in STEP 1, etching said bottom anti-reflective coating (BARC) layer by flowing bromine species gas and oxygen species gas, and applying a first TCP Power and a first Bias power; b) in STEP 2, etching said hard mask by flowing a flouorocarbon gas; and applying a second TCP Power and second Bias power; c) in STEP 3--stripping said bottom anti-reflective coating (BARC) layer by flowing oxygen and applying a third TCP Power and a third Bias power; d) in STEP 4--etching said polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a fourth TCP Power and a fourth Bias power.
Claim 3
Dependent Claim 27 words
The method of claim 1 wherein said gate oxide layer composed of silicon oxide having a thickness in a range of between about 20 and 100 Å.
Claim 4
Dependent Claim 22 words
The method of claim 1 wherein said polysilicon layer having a thickness in a range of between about 1000 and 3000 Å.
Claim 5
Dependent Claim 40 words
The method of claim 1 wherein said hard mask layer composed of a material selected from the group consisting of silicon nitride, oxynitride; and silicon oxide and having a thickness in a range of between about 200 and 3000 Å.
Claim 6
Dependent Claim 36 words
The method of claim 1 wherein said hard mask layer composed of a material selected from the group consisting of silicon oxide and having a thickness in a range of between about 200 and 3000 Å.
Claim 7
Dependent Claim 19 words
The method of claim 1 wherein said bottom anti-reflective coating (BARC) layer composed of polymer resin with photo compounds.
Claim 8
Dependent Claim 36 words
The method of claim 1 wherein said resist layer having a thickness in a range of between about 6000 and 13000 Å and a width in a range of between about 0.14 μm and 0.25 μm.
Claim 9
Dependent Claim 56 words
The method of claim 1 wherein said step 1 further comprises the following conditions: a pressure between about 5 and 30 torr; a First TCP power between 100 and 300 W; a Bias power 100 and 300 W; a HBr flow between 50 and 60 sccm; a O 2 flow between about 5 and 30 sccm.
Claim 10
Dependent Claim 53 words
The method of claim 1 wherein said step 2 further comprises the following conditions: a pressure between about 5 and 30 torr; a second TCP power between about 100 and 400 W; a Second Bias power between 100 and 300 W; a C 2 F 6 flow between about 50 and 120 sccm.
Claim 11
Dependent Claim 52 words
The method of claim 1 wherein Said step 3 further comprises the following conditions: a pressure between about 5 and 80 torr, a third TCP power between about 100 and 400 W; a third bias power between about 0 and 200 W; a O 2 flow between about 100 and 500 sccm.
Claim 12
Dependent Claim 70 words
The method of claim 1 wherein said step 4 further comprises the following conditions: a pressure between about 5 and 30 mTorr; said Fourth TCP power between about 100 and 300 watts; a Bias power between about 100 and 300 W; a Cl 2 flow between about 30 and 100 sccm, a HeO 2 flow between about 0 and 20 sccm; a HBr flow between about 100 and 400 sccm.
Claim 13
Independent Claim 328 words
A method of fabricating a submicron polysilicon gate; comprising the steps of: forming sequentially a gate oxide layer, a polysilicon layer, a hard mask layer composed of silicon oxide, and a bottom anti-reflective coating (BARC) layer over a substrate; forming a resist layer over said bottom anti-reflective coating (BARC) layer; said resist layer defining said polysilicon gate; placing said substrate into a polysilicon high density plasma etcher and performing insitu the following steps: a) STEP 1, etching said bottom anti-reflective coating (BARC) layer by flowing HBr and O 2 gasses, and applying a first TCP Power and a first Bias power; said step 1 further comprises the following conditions: a pressure between about 5 and 30 torr; said first TCP power between 100 and 300 W; said first Bias power 100 and 300 W; b) in STEP 2--etching said hard mask by flowing a flouorocarbon gas; and applying a second TCP Power and second Bias power; said step 2 further comprises the following conditions: a pressure between about 5 and 30 torr; a second TCP power between about 100 and 400 W; a Second Bias power between 100 and 300 W; c) in STEP 3--stripping said bottom anti-reflective coating (BARC) layer by flowing oxygen and applying a third TCP Power and a third Bias power, said step 3 further comprises the following conditions: a pressure between about 5 and 80 torr, a third TCP power between about 100 and 400 W; a third bias power between about 0 and 200 W; a O 2 flow between about 100 and 500 sccm; and d) in STEP 4--etching said polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a fourth TCP Power and a fourth Bias power; said step 4 further comprises the following conditions: a pressure between about 5 and 30 mtorr; said Fourth TCP power between about 100 and 300 watts; said fourth Bias power between about 100 and 300 W.
Claim 14
Independent Claim 328 words
A method of fabricating a submicron polysilicon gate; comprising the steps of: forming sequentially a gate oxide layer, a polysilicon layer, a hard mask layer composed of silicon oxide, and a bottom anti-reflective coating (BARC) layer over a substrate; forming a resist layer over said bottom anti-reflective coating (BARC) layer; said resist layer defining said polysilicon gate; placing said substrate into a polysilicon high density plasma etcher and performing insitu the following steps: a) STEP 1, etching said bottom anti-reflective coating (BARC) layer by flowing HBr and O 2 gasses, and applying a first TCP Power and a first Bias power; said step 1 further comprises the following conditions: a pressure between about 5 and 30 torr; said first TCP power between 100 and 300 W; said first Bias power 100 and 300 W; b) in STEP 2--etching said hard mask by flowing a flouorocarbon gas; and applying a second TCP Power and second Bias power; said step 2 further comprises the following conditions: a pressure between about 5 and 30 torr; a second TCP power between about 100 and 400 W; a Second Bias power between 100 and 300 W; c) in STEP 3--stripping said bottom anti-reflective coating (BARC) layer by flowing oxygen and applying a third TCP Power and a third Bias power, said step 3 further comprises the following conditions: a pressure between about 5 and 80 torr, a third TCP power between about 100 and 400 W; a third bias power between about 0 and 200 W; a O 2 flow between about 100 and 500 sccm; and d) in STEP 4--etching said polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a fourth TCP Power and a fourth Bias power; said step 4 further comprises the following conditions: a pressure between about 5 and 30 mtorr; said Fourth TCP power between about 100 and 300 watts; said fourth Bias power between about 100 and 300 W.
Claim 15
Dependent Claim 22 words
The method of claim 12 wherein STEP 2 further comprises a C 2 F 6 flow between about 50 and 120 sccm.
Claim 16
Dependent Claim 28 words
The method of claim 12 wherein STEP 3 further comprises a HBr flow between 50 and 60 sccm; a O 2 flow between about 5 and 30 sccm.
Claim 17
Dependent Claim 39 words
The method of claim 12 wherein STEP 3 further comprising a Cl 2 flow between about 30 and 100 sccm, a HeO 2 flow between about 0 and 20 sccm; a HBr flow between about 100 and 400 sccm.
Claim 18
Independent Claim 303 words
A method of fabricating a submicron polysilicon gate; comprising the steps of: forming sequentially a gate oxide layer, a polysilicon layer, a hard mask layer composed of silicon oxide, and a bottom anti-reflective coating (BARC) layer over a substrate; forming a resist layer over said bottom anti-reflective coating (BARC) layer; said resist layer defining said polysilicon gate; placing said substrate into a polysilicon high density plasma etcher and performing insitu the following steps: (1) in STEP 1, etching said bottom anti-reflective coating (BARC) layer at the following conditions: a pressure between about 5 and 30 torr; a first TCP power between 100 and 300 W; a Bias power 100 and 300 W; a HBr flow between 50 and 60 sccm; a O 2 flow between about 5 and 30 sccm; (2) in STEP 2, etching said hard mask at the following conditions: a pressure between about 5 and 30 torr; a second TCP power between about 100 and 400 W; a Second Bias power between 100 and 300 W; a C 2 F 6 flow between about 50 and 120 sccm; (3) in STEP 3, stripping said bottom anti-reflective coating (BARC) layer at the following conditions: a pressure between about 5 and 80 torr, a third TCP power between about 100 and 400 W; a third bias power between about 0 and 200 W; a O 2 flow between about 100 and 500 sccm; and (4) in STEP 4, etching said polysilicon layer at the following conditions: a pressure between about 5 and 30 mTorr; a fourth TCP power between about 100 and 300 watts; a Bias power between about 100 and 300 W; a Cl 2 flow between about 30 and 100 sccm, a HeO 2 flow between about 0 and 20 sccm; a HBr flow between about 100 and 400 sccm.
Claim 19
Independent Claim 303 words
A method of fabricating a submicron polysilicon gate; comprising the steps of: forming sequentially a gate oxide layer, a polysilicon layer, a hard mask layer composed of silicon oxide, and a bottom anti-reflective coating (BARC) layer over a substrate; forming a resist layer over said bottom anti-reflective coating (BARC) layer; said resist layer defining said polysilicon gate; placing said substrate into a polysilicon high density plasma etcher and performing insitu the following steps: (1) in STEP 1, etching said bottom anti-reflective coating (BARC) layer at the following conditions: a pressure between about 5 and 30 torr; a first TCP power between 100 and 300 W; a Bias power 100 and 300 W; a HBr flow between 50 and 60 sccm; a O 2 flow between about 5 and 30 sccm; (2) in STEP 2, etching said hard mask at the following conditions: a pressure between about 5 and 30 torr; a second TCP power between about 100 and 400 W; a Second Bias power between 100 and 300 W; a C 2 F 6 flow between about 50 and 120 sccm; (3) in STEP 3, stripping said bottom anti-reflective coating (BARC) layer at the following conditions: a pressure between about 5 and 80 torr, a third TCP power between about 100 and 400 W; a third bias power between about 0 and 200 W; a O 2 flow between about 100 and 500 sccm; and (4) in STEP 4, etching said polysilicon layer at the following conditions: a pressure between about 5 and 30 mTorr; a fourth TCP power between about 100 and 300 watts; a Bias power between about 100 and 300 W; a Cl 2 flow between about 30 and 100 sccm, a HeO 2 flow between about 0 and 20 sccm; a HBr flow between about 100 and 400 sccm.

References Cited (Backward Citations)

US5094712A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-03-14 2003-09-13 2004-03-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-03-14 2007-09-13 2008-03-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-03-14 2011-09-13 2012-03-14 $7700.00 Window Closed / Lapsed

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