US5545588A
Expired / Lapsed
US
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Method of using disposable hard mask for gate critical dimension control
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1995-05-05
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Granted: 1996-08-13
•
Expires: 2015-05-05
Abstract
Abstract A new method of controlling the critical dimension width of polysilicon by using a disposable hard mask is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A layer of polysilicon is deposited over the uneven surface of the substrate. The polysilicon layer is covered with a spin-on-glass layer wherein the spin-on-glass material planarizes the surface of the underlying topography. A semiconductor layer is deposited over the surface of the planarization layer to act as a hard mask wherein the semiconductor layer is opaque to actinic light. The semiconductor layer is covered with a uniform thickness layer of photoresist. The photoresist layer is exposed to actinic light wherein the semiconductor layer prevents reflection of the actinic light from its surface. The photoresist layer is developed and patterned to form the desired photoresist mask for the polysilicon layer. The semiconductor layer, the spin-on-glass layer, and the polysilicon layer not covered by the photoresist mask are anisotropically etched away to form polysilicon gate electrodes and interconnection lines. The photoresist mask, the hard mask, and the spin-on-glass layer are removed to complete the formation of polysilicon gate electrodes and interconnection lines having uniform critical dimension in the fabrication of an integrated circuit.
Inventors
- 👤 Chue-San Yoo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:01
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10P; H10P50/00; H10P50/71; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/95; Y10S438/952
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
249 words
A method of providing a uniform critical dimension of gate electrodes and interconnection lines during photoetching in the fabrication of an integrated circuit comprising: providing field oxide isolation areas surrounding bare active areas in and on a semiconductor substrate wherein the surface of said substrate has an uneven topography; growing a gate silicon oxide layer on the surface of said field oxide areas and said active areas of said semiconductor substrate; depositing a conducting layer over said gate silicon oxide layer; covering said conducting layer with a planarization layer wherein said planarization layer planarizes the surface of said substrate; depositing an anti-reflection layer over the surface of said planarization layer wherein said anti-reflection layer forms a hard mask which is opaque to actinic light; covering said hard mask with a uniform thickness layer of photoresist; exposing said photoresist layer to actinic light wherein said hard mask prevents reflection of said actinic light from its surface and developing and patterning said photoresist layer to form a photoresist mask for said conducting layer; anisotropically etching away said hard mask, said planarization layer, and said conducting layer not covered by said photoresist mask to form said gate electrodes and interconnection lines wherein the width of said gate electrodes and interconnection lines is said critical dimension; and removing said photoresist mask, remaining said hard mask, and remaining said planarization layer to complete the formation of said gate electrodes and interconnection lines having said uniform critical dimension in the fabrication of said integrated circuit.
Claim 2
Independent Claim
249 words
A method of providing a uniform critical dimension of gate electrodes and interconnection lines during photoetching in the fabrication of an integrated circuit comprising: providing field oxide isolation areas surrounding bare active areas in and on a semiconductor substrate wherein the surface of said substrate has an uneven topography; growing a gate silicon oxide layer on the surface of said field oxide areas and said active areas of said semiconductor substrate; depositing a conducting layer over said gate silicon oxide layer; covering said conducting layer with a planarization layer wherein said planarization layer planarizes the surface of said substrate; depositing an anti-reflection layer over the surface of said planarization layer wherein said anti-reflection layer forms a hard mask which is opaque to actinic light; covering said hard mask with a uniform thickness layer of photoresist; exposing said photoresist layer to actinic light wherein said hard mask prevents reflection of said actinic light from its surface and developing and patterning said photoresist layer to form a photoresist mask for said conducting layer; anisotropically etching away said hard mask, said planarization layer, and said conducting layer not covered by said photoresist mask to form said gate electrodes and interconnection lines wherein the width of said gate electrodes and interconnection lines is said critical dimension; and removing said photoresist mask, remaining said hard mask, and remaining said planarization layer to complete the formation of said gate electrodes and interconnection lines having said uniform critical dimension in the fabrication of said integrated circuit.
Claim 3
Dependent Claim
22 words
A method according to claim 1 wherein said uneven topography has a vertical height difference of between about 1000 and 4000 Angstroms.
Claim 4
Dependent Claim
22 words
A method according to claim 1 wherein said conducting layer comprises polysilicon having a thickness of between about 2000 and 4000 Angstroms.
Claim 5
Dependent Claim
22 words
A method according to claim 1 wherein said conducting layer comprises polycide having a thickness of between about 2000 and 4000 Angstroms.
Claim 6
Dependent Claim
23 words
A method according to claim 1 wherein said planarization layer comprises spin-on-glass coated to a thickness of between about 1000 and 4000 Angstroms.
Claim 7
Dependent Claim
13 words
A method according to claim 5 wherein said spin-on-glass material is a silicate.
Claim 8
Dependent Claim
13 words
A method according to claim 5 wherein said spin-on-glass material is a siloxane.
Claim 9
Dependent Claim
26 words
A method according to claim 5 wherein said spin-on-glass layer is baked at between about 200° and 420° C. for between about 15 and 40 minutes.
Claim 10
Dependent Claim
31 words
A method according to claim 1 wherein said planarization layer comprises phosphosilicate glass deposited to a thickness of between about 1000 and 4000 Angstroms and wherein said planarization layer is reflowed.
Claim 11
Dependent Claim
31 words
A method according to claim 1 wherein said planarization layer comprises borophosphosilicate glass deposited to a thickness of between about 1000 and 4000 Angstroms and wherein said planarization layer is reflowed.
Claim 12
Dependent Claim
48 words
A method according to claim 1 wherein said planarization layer comprises a double layer of borophosphosilicate glass deposited to a thickness of between about 1000 and 4000 Angstroms and tetraethoxysilane deposited to a thickness of between about 1000 and 4000 Angstroms and wherein said double layer is reflowed.
Claim 13
Dependent Claim
25 words
A method according to claim 1 wherein said anti-reflection layer comprises titanium nitride sputter deposited to a thickness of between about 100 and 400 Angstroms.
Claim 14
Dependent Claim
25 words
A method according to claim 1 wherein said anti-reflection layer comprises amorphous silicon sputter deposited to a thickness of between about 100 and 400 Angstroms.
Claim 15
Dependent Claim
21 words
A method according to claim 1 wherein remaining said hard mask is removed by a solution of ammonium and hydrogen peroxide.
Claim 16
Dependent Claim
18 words
A method according to claim 5 wherein remaining said planarization layer is removed by a hydrofluoric acid solution.
Claim 17
Dependent Claim
18 words
A method according to claim 9 wherein remaining said planarization layer is removed by a hydrofluoric acid solution.
Claim 18
Dependent Claim
16 words
A method according to claim 9 wherein remaining said planarization layer is removed by plasma etching.
Claim 19
Dependent Claim
18 words
A method according to claim 10 wherein remaining said planarization layer is removed by a hydrofluoric acid solution.
Claim 20
Dependent Claim
16 words
A method according to claim 10 wherein remaining said planarization layer is removed by plasma etching.
Claim 21
Dependent Claim
18 words
A method according to claim 11 wherein remaining said planarization layer is removed by a hydrofluoric acid solution.
Claim 22
Dependent Claim
16 words
A method according to claim 11 wherein remaining said planarization layer is removed by plasma etching.
Claim 23
Independent Claim
249 words
A method of providing a uniform critical dimension of gate electrodes and interconnection lines during photoetching in the fabrication of an integrated circuit comprising: providing field oxide isolation areas surrounding bare active areas in and on a semiconductor substrate wherein the surface of said substrate has an uneven topography; growing a gate silicon oxide layer on the surface of said field oxide areas and said active areas of said semiconductor substrate; depositing a conducting layer over said gate silicon oxide layer; depositing an anti-reflection layer over the surface of said conducting layer wherein said anti-reflection layer forms a hard mask which is opaque to actinic light; covering said hard mask with a planarization layer wherein said planarization layer planarizes the surface of said substrate; covering said planarization layer with a uniform thickness layer of photoresist; exposing said photoresist layer to actinic light wherein said hard mask prevents reflection of said actinic light from its surface and developing and patterning said photoresist layer to form a photoresist mask for said conducting layer; anisotropically etching away said planarization layer, said hard mask, and said conducting layer not covered by said photoresist mask to form said gate electrodes and interconnection lines wherein the width of said gate electrodes and interconnection lines is said critical dimension; and removing said photoresist mask, remaining said planarization layer, and remaining said hard mask to complete the formation of said gate electrodes and interconnection lines having said uniform critical dimension in the fabrication of said integrated circuit.
Claim 24
Independent Claim
249 words
A method of providing a uniform critical dimension of gate electrodes and interconnection lines during photoetching in the fabrication of an integrated circuit comprising: providing field oxide isolation areas surrounding bare active areas in and on a semiconductor substrate wherein the surface of said substrate has an uneven topography; growing a gate silicon oxide layer on the surface of said field oxide areas and said active areas of said semiconductor substrate; depositing a conducting layer over said gate silicon oxide layer; depositing an anti-reflection layer over the surface of said conducting layer wherein said anti-reflection layer forms a hard mask which is opaque to actinic light; covering said hard mask with a planarization layer wherein said planarization layer planarizes the surface of said substrate; covering said planarization layer with a uniform thickness layer of photoresist; exposing said photoresist layer to actinic light wherein said hard mask prevents reflection of said actinic light from its surface and developing and patterning said photoresist layer to form a photoresist mask for said conducting layer; anisotropically etching away said planarization layer, said hard mask, and said conducting layer not covered by said photoresist mask to form said gate electrodes and interconnection lines wherein the width of said gate electrodes and interconnection lines is said critical dimension; and removing said photoresist mask, remaining said planarization layer, and remaining said hard mask to complete the formation of said gate electrodes and interconnection lines having said uniform critical dimension in the fabrication of said integrated circuit.
Claim 25
Dependent Claim
22 words
A method according to claim 22 wherein said uneven topography has a vertical height difference of between about 1000 and 4000 Angstroms.
Claim 26
Dependent Claim
22 words
A method according to claim 22 wherein said conducting layer comprises polysilicon having a thickness of between about 2000 and 4000 Angstroms.
Claim 27
Dependent Claim
22 words
A method according to claim 22 wherein said conducting layer comprises polycide having a thickness of between about 2000 and 4000 Angstroms.
Claim 28
Dependent Claim
23 words
A method according to claim 22 wherein said planarization layer comprises spin-on-glass coated to a thickness of between about 1000 and 4000 Angstroms.
Claim 29
Dependent Claim
26 words
A method according to claim 26 wherein said spin-on-glass layer is baked at between about 200° and 420° C. for between about 15 and 40 minutes.
Claim 30
Dependent Claim
31 words
A method according to claim 22 wherein said planarization layer comprises phosphosilicate glass deposited to a thickness of between about 1000 and 4000 Angstroms and wherein said planarization layer is reflowed.
Claim 31
Dependent Claim
31 words
A method according to claim 22 wherein said planarization layer comprises borophosphosilicate glass deposited to a thickness of between about 1000 and 4000 Angstroms and wherein said planarization layer is reflowed.
Claim 32
Dependent Claim
48 words
A method according to claim 22 wherein said planarization layer comprises a double layer of borophosphosilicate glass deposited to a thickness of between about 1000 and 4000 Angstroms and tetraethoxysilane deposited to a thickness of between about 1000 and 4000 Angstroms and wherein said double layer is reflowed.
Claim 33
Dependent Claim
25 words
A method according to claim 22 wherein said anti-reflection layer comprises titanium nitride sputter deposited to a thickness of between about 100 and 400 Angstroms.
Claim 34
Dependent Claim
25 words
A method according to claim 22 wherein said anti-reflection layer comprises amorphous silicon sputter deposited to a thickness of between about 100 and 400 Angstroms.
Claim 35
Dependent Claim
21 words
A method according to claim 22 wherein remaining said hard mask is removed by a solution of ammonium and hydrogen peroxide.
Claim 36
Independent Claim
244 words
A method of providing a uniform critical dimension of gate electrodes and interconnection lines during etching in the fabrication of an integrated circuit comprising: providing field oxide isolation areas surrounding bare active areas in and on a semiconductor substrate wherein the surface of said substrate has an uneven topography; growing a gate silicon oxide layer on the surface of said field oxide areas and said active areas of said semiconductor substrate; depositing a conducting layer over said gate silicon oxide layer; covering said conducting layer with a spin-on-glass layer wherein said spin-on-glass layer planarizes the surface of said substrate; depositing a titanium layer over the surface of said spin-on-glass layer wherein said titanium layer is opaque to actinic light; covering said titanium layer with a uniform thickness layer of photoresist; exposing said photoresist layer to actinic light wherein said titanium layer prevents reflection of said actinic light from its surface and developing and patterning said photoresist layer to form a photoresist mask for said conducting layer; anisotropically etching away said titanium layer, said spin-on-glass layer, and said conducting layer not covered by said photoresist mask to form said gate electrodes and interconnection lines wherein the width of said gate electrodes and interconnection lines is said critical dimension; and removing said photoresist mask, remaining said titanium layer, and remaining said spin-on-glass layer to complete the formation of said gate electrodes and interconnection lines having said uniform critical dimension in the fabrication of said integrated circuit.
Claim 37
Independent Claim
244 words
A method of providing a uniform critical dimension of gate electrodes and interconnection lines during etching in the fabrication of an integrated circuit comprising: providing field oxide isolation areas surrounding bare active areas in and on a semiconductor substrate wherein the surface of said substrate has an uneven topography; growing a gate silicon oxide layer on the surface of said field oxide areas and said active areas of said semiconductor substrate; depositing a conducting layer over said gate silicon oxide layer; covering said conducting layer with a spin-on-glass layer wherein said spin-on-glass layer planarizes the surface of said substrate; depositing a titanium layer over the surface of said spin-on-glass layer wherein said titanium layer is opaque to actinic light; covering said titanium layer with a uniform thickness layer of photoresist; exposing said photoresist layer to actinic light wherein said titanium layer prevents reflection of said actinic light from its surface and developing and patterning said photoresist layer to form a photoresist mask for said conducting layer; anisotropically etching away said titanium layer, said spin-on-glass layer, and said conducting layer not covered by said photoresist mask to form said gate electrodes and interconnection lines wherein the width of said gate electrodes and interconnection lines is said critical dimension; and removing said photoresist mask, remaining said titanium layer, and remaining said spin-on-glass layer to complete the formation of said gate electrodes and interconnection lines having said uniform critical dimension in the fabrication of said integrated circuit.
Claim 38
Dependent Claim
22 words
A method according to claim 34 wherein said uneven topography has a vertical height difference of between about 1000 and 4000 Angstroms.
Claim 39
Dependent Claim
22 words
A method according to claim 34 wherein said conducting layer comprises polysilicon having a thickness of between about 2000 and 4000 Angstroms.
Claim 40
Dependent Claim
22 words
A method according to claim 34 wherein said conducting layer comprises polycide having a thickness of between about 2000 and 4000 Angstroms.
Claim 41
Dependent Claim
24 words
A method according to claim 34 wherein said spin-on-glass material is a silicate coated to a thickness of between about 1000 and 4000 Angstroms.
Claim 42
Dependent Claim
24 words
A method according to claim 34 wherein said spin-on-glass material is a siloxane coated to a thickness of between about 1000 and 4000 Angstroms.
Claim 43
Dependent Claim
26 words
A method according to claim 34 wherein said spin-on-glass layer is baked at between about 200° and 420° C. for between about 15 and 40 minutes.
Claim 44
Dependent Claim
23 words
A method according to claim 34 wherein said titanium layer is sputter deposited to a thickness of between about 100 and 400 Angstroms.
Claim 45
Dependent Claim
21 words
A method according to claim 34 wherein remaining said titanium layer is removed by a solution of ammonium and hydrogen peroxide.
Claim 46
Dependent Claim
18 words
A method according to claim 34 wherein remaining said spin-on-glass layer is removed by a hydrofluoric acid solution.
Claim 47
Dependent Claim
24 words
A method according to claim 1 wherein said anti-reflection layer comprises titanium sputter deposited to a thickness of between about 100 and 400 Angstroms.
Claim 48
Dependent Claim
49 words
A method according to claim 22 wherein said planarization layer comprises a double layer of borophosphosilicate glass deposited to a thickness of between about 1000 and 4000 Angstroms and silicon oxide deposited to a thickness of between about 1000 and 4000 Angstroms and wherein said double layer is reflowed.
References Cited (Backward Citations)
US5219788A
Cited
US5350486A
Cited
US5354713A
Cited
JPH05206125A
Cited
US5302538A
Cited
US5324689A
Cited
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