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US5350486A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor planarization process

Assignee: STMicroelectronics lnc USA
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Filing: 1993-05-20
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Granted: 1994-09-27
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Expires: 2013-05-20
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Abstract

Abstract A method for planarizing an integrated circuit structure having a glass layer overlying an oxide layer of an integrated circuit is presented. The method includes the steps of selectively etching portions of the glass structure that overlie portions of the oxide layer that have higher elevations than other portions of the oxide layer, and then etching the glass layer overall. The etching step includes forming a layer of photoresist over the glass layer, exposing selected areas of the photoresist over the portions of the oxide layer that have higher elevations than other portions of the oxide layer, removing the exposed areas of the photoresist, and etching the glass layer within the removed areas of the photoresist. The mask used in patterning the photoresist can be the same mask, or its negative, that is used in forming the metalization layer over which the oxide and glass layers have been formed. Additionally, an integrated circuit structure is presented that includes a substrate in which integrated circuit elements are constructed, a first interconnection metalization over the substrate interconnecting selected ones of the integrated circuit elements, and an oxide layer over the substrate and the first metal interconnection pattern. A glass layer over the oxide layer is substantially planar between portions that overlie the metalization and portions that do not over lie the metalization.

Inventors

  • 👤 Kuei-Wu Huang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 02:46
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10P95/066; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 87 words
A method for planarizing an integrated circuit structure having a isolating layer overlying an oxide layer of an integrated circuit, comprising: forming a layer of photoresist over said isolating layer; exposing selected areas of said photoresist over portions of said oxide layer that have higher elevations than other portions of said oxide layer; removing said exposed areas of said photoresist; at least partially etching said isolating layer that is within said removed areas of said photoresist; removing said layer of photoresist; and etching said isolating layer overall.
Claim 2
Independent Claim 87 words
A method for planarizing an integrated circuit structure having a isolating layer overlying an oxide layer of an integrated circuit, comprising: forming a layer of photoresist over said isolating layer; exposing selected areas of said photoresist over portions of said oxide layer that have higher elevations than other portions of said oxide layer; removing said exposed areas of said photoresist; at least partially etching said isolating layer that is within said removed areas of said photoresist; removing said layer of photoresist; and etching said isolating layer overall.
Claim 3
Dependent Claim 17 words
The method of claim 1 wherein said oxide layer has been deposited by plasma-enhanced oxide deposition techniques.
Claim 4
Dependent Claim 16 words
The method of claim 1 wherein said isolating layer has been formed by spin-on glass techniques.
Claim 5
Dependent Claim 13 words
The method of claim 1 further comprising providing metal layers under said oxide.
Claim 6
Dependent Claim 53 words
The method of claim 4 wherein said step of exposing selected areas of said photoresist over said portions of said oxide layer that overlie said metal layers comprises providing a mask that is a negative of a mask used to form said metal layers, and exposing said layer of photoresist through said mask.
Claim 7
Dependent Claim 73 words
The method of claim 4 wherein said step of forming a layer of photoresist over said isolating layer comprises forming a layer of positive resist over said isolating layer, and wherein said step of exposing selected areas of said photoresist over said portions of said oxide layer that overlie said metal layers comprises utilizing a mask that was used to form said metal layers, and exposing said layer of photoresist through said mask.
Claim 8
Independent Claim 71 words
A method for manufacturing an integrated circuit, comprising: providing a substrate; forming a first metal interconnection pattern over said substrate for interconnecting selected components of said integrated circuit; forming an oxide layer over said substrate and said first metal interconnection pattern; forming a layer of glass over said oxide layer; selectively etching portions of said glass and oxide layers that overlie said metal interconnection pattern; and etching said glass layer overall.
Claim 9
Independent Claim 71 words
A method for manufacturing an integrated circuit, comprising: providing a substrate; forming a first metal interconnection pattern over said substrate for interconnecting selected components of said integrated circuit; forming an oxide layer over said substrate and said first metal interconnection pattern; forming a layer of glass over said oxide layer; selectively etching portions of said glass and oxide layers that overlie said metal interconnection pattern; and etching said glass layer overall.
Claim 10
Dependent Claim 35 words
The method of claim 7 wherein said step of forming an oxide layer over said substrate and said first metal interconnection pattern comprises forming CVD oxide over said substrate and said first metal interconnection pattern.
Claim 11
Dependent Claim 29 words
The method of claim 8 wherein said step of forming a layer of glass over said oxide layer comprises forming a layer of spin-on glass over said oxide layer.
Claim 12
Dependent Claim 58 words
The method of claim 9 wherein said step of selectively etching portions of said glass comprises forming a layer of photoresist over said glass layer, exposing selected areas of said photoresist over said first metal interconnection pattern, removing said exposed areas of said photoresist, and etching said glass and oxide layers within said removed areas of said photoresist.
Claim 13
Dependent Claim 43 words
The method of claim 10 wherein said step of etching said glass and oxide layers within said removed areas of said photoresist comprises etching between about 10 and 90 percent of the thickness of said glass and oxide layers within said removed areas.
Claim 14
Dependent Claim 64 words
The method of claim 10 wherein said step of forming a layer of photoresist comprises forming a layer of positive photoresist, and wherein said step of exposing selected areas of said photoresist over said first metal interconnection pattern comprises providing a mask that is a negative of a mask used to form said metal layers, and exposing said layer of photoresist through said mask.
Claim 15
Dependent Claim 57 words
The method of claim 10 wherein said step of forming a layer of photoresist comprises forming a layer of negative photoresist, and wherein said step of exposing selected areas of said photoresist over said first metal interconnection pattern comprises providing a mask used to form said metal layers, and exposing said layer of photoresist through said mask.
Claim 16
Dependent Claim 17 words
The method of claim 10 further comprising forming a second level of metal on the glass layer.
Claim 17
Dependent Claim 50 words
The method of claim 11 wherein said step of etching between about 10 and 90 percent of the thickness of said glass and oxide layers within said removed areas comprises etching between about 33 and 66 percent of the thickness of said glass and oxide layers within said removed areas.

References Cited (Backward Citations)

JPS61276347A Cited
US4662064A Cited
US4775550A Cited
US4676867A Cited
US4978419A Cited
JPS63269535A Cited
JPS6417431A Cited
US5139608A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-09-26 1998-03-28 1998-09-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-09-26 2002-03-28 2002-09-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-09-26 2006-03-28 2006-09-27 $7700.00 Window Closed / Lapsed

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