US4662064A
Expired / Lapsed
US
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Method of forming multi-level metallization
Assignee: Intersil Corp
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Filing: 1985-08-05
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Granted: 1987-05-05
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Expires: 2005-08-05
Abstract
Abstract A multi-level metallization is formed by forming a patterned first level metallization layer on the surface of an isolating layer on a substrate of semiconductor material. A thick planarizing layer, preferably of a glass, is applied over the first level metallization layer and the exposed areas of the insulating layer with the planarizing layer bearing depressions in its surface over the exposed areas of the insulating layer. A photoresist layer is formed on the planarizing layer in the depressions in its surface with the portions of the planarizing layer over the first level metallization layer being exposed. The exposed areas of the planarizing layer are isotropically etched until the surface of the planarizing layer is substantially planar with the bottom of the deepest depression in the planarizing layer. Any photoresist material is removed and the planarizing layer is isotropically etched until its surface is substantially planar with the surface of the first level metallization layer. An inter-level insulating layer is applied over the planarized surfaces of the first level metallization layer at the planarizing layer, and a second level metallization layer is applied over the inter-level insulating layer.
Inventors
- 👤 Sheng T. Hsu
- 👤 Doris W. Flatley
- 👤 Ronald J. Johansson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:49
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10P95/066
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
187 words
In a method of forming multi-level metallization on a semiconductor substrate, the steps of: (a) forming a patterned first layer of a conductive material on a layer of insulating material which is over a surface of the substrate, (b) providing a planarizing layer of insulating material over the first conductive layer and any exposed portion of the insulating layer, said planarizing layer being twice the thickness of the first conductive layer and having depressions in its surface over the said exposed portions of the insulating layer, (c) forming a layer of a resist material on the planarizing layer over the depressions in the planarizing layer leaving exposed the portions of the planarizing layer over the first conductive layer, (d) etching the exposed portions of the planarizing layer so that the surface of the planarizing layer is substantially planar with the portions of the planarizing layer at the bottom of the deepest depression, (e) removing any of the resist layer on the planarizing layer, and then (f) etching the entire surface of the planarizing layer until it is substantially planar with the surface of the first conductive layer.
Claim 2
Dependent Claim
187 words
In a method of forming multi-level metallization on a semiconductor substrate, the steps of: (a) forming a patterned first layer of a conductive material on a layer of insulating material which is over a surface of the substrate, (b) providing a planarizing layer of insulating material over the first conductive layer and any exposed portion of the insulating layer, said planarizing layer being twice the thickness of the first conductive layer and having depressions in its surface over the said exposed portions of the insulating layer, (c) forming a layer of a resist material on the planarizing layer over the depressions in the planarizing layer leaving exposed the portions of the planarizing layer over the first conductive layer, (d) etching the exposed portions of the planarizing layer so that the surface of the planarizing layer is substantially planar with the portions of the planarizing layer at the bottom of the deepest depression, (e) removing any of the resist layer on the planarizing layer, and then (f) etching the entire surface of the planarizing layer until it is substantially planar with the surface of the first conductive layer.
Claim 3
Dependent Claim
17 words
A method in accordance with claim 1 wherein the planarizing layer is etched by an isotropic etch.
Claim 4
Dependent Claim
31 words
A method in accordance with claim 2 wherein the thickness of the planarizing layer at the bottom of the deepest depression is thicker than the thickness of the first conductive layer.
Claim 5
Dependent Claim
15 words
A method in accordance with claim 3 wherein the planarizing layer is a doped glass.
Claim 6
Independent Claim
82 words
A method in accordance with claim, 2 wherein the patterned first conductive layer is formed by applying a layer of the conductive material over the surface of the insulating layer, applying a photoresist layer on the conductive layer, exposing the photoresist layer using a mask having opaque and transparent areas one of which corresponds to the pattern desired for the conductive layer, developing the photoresist layer to expose portions of the conductive layer, and removing the undesired portions of the conductive layer.
Claim 7
Dependent Claim
66 words
A method in accordance with claim 5 wherein the photoresist over the planarizing layer is formed by applying a layer of photoresist material over the entire surface of the planarizing layer, exposing the photoresist layer using a mask which is the reverse of the mask used to form the patterned first conductive layer, and then developing the photoresist layer to leave the portions in the depressions.
Claim 8
Dependent Claim
76 words
A method in accordance with claim 5 wherein the photoresist over the planarizing layer is formed by applying a layer of a photoresist material of the opposite type to that used to pattern the first conductive layer over the entire surface of the planarizing layer, used a mask substantially the same as that used to pattern the first conductive layer, exposing the photoresist layer, and then developing the photoresist layer to leave portions in the depressions.
Claim 9
Dependent Claim
41 words
A method in accordance with claim 1 including the additional step of applying an inter-level insulating layer over the planarize surfaces of the first conductive layer and the planarizing layer, and forming a second conductive layer over the inter-level insulating layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-04 | 1990-11-03 | 1991-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-04 | 1994-11-03 | 1995-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-04 | 1998-11-03 | 1999-05-05 | $7700.00 | Window Closed / Lapsed |