Method for interconnecting metallic layers

Claim 3

A method as in claim 1, wherein a second insulating layer is applied over the first insulating layer after step (d) and before step (e).

Claim 4

A method as in claim 1, wherein a third insulating layer is applied over the second insulating layer after step (e), and wherein the vias are further etched to define a stepped configuration.

Claim 5

A method as in claim 3, wherein the step is formed in the second insulating layer.

Claim 6

A method as in claim 1, wherein steps (b) through (g) are repeated to add additional metal layers on the device.

Claim 7

A method as in claim 1, wherein the metal layers are aluminum, aluminum-copper, aluminum-silicon, or aluminum-copper-silicon.

Claim 8

A method as in claim 1, wherein the insulating layers are silicon dioxide or phosphorous-silicon dioxide.

Claim 9

A method as in claim 7, wherein the insulating layers are deposited by pyrolysis of silane or silane in the presence of phosphine.

Claim 10

A method as in claim 1, wherein the vias are formed by plasma etching in step (e).

Claim 11

A method as in claim 1, wherein the planarization layer and first insulating layer are plasma etched in step (d).

Claim 12

A method as in claim 9, wherein the same etchant is used in steps (d) and (e).

Claim 13

A method as in claim 11, wherein the etchant is substantially anisotropic and is selected to have an etch ratio of 1.6:1.0 (insulating layer:planarization layer).

Claim 14

A method as in claim 1, wherein the planarization layer is photoresist.

Claim 15

An improved method for forming multiple interconnect layers on a semiconductor device, said method including the steps of: (a) defining a first metal layer, having a preselected interconnect pattern, on the device; (b) applying a first insulating layer of the first metal layer; (c) forming vias through the first insulating layer; and (d) defining a second metal layer, having a preselected interconnect pattern, over the first insulating layer; wherein the improvement comprises: planarizing the first insulating layer by applying a planarization layer over the first insulating layer and etching both the planarization layer and the first insulating layer to impart a smoothed profile to the first insulating layer; applying a second insulating layer over the smoothed first insulating layer; forming the vias through both the first and second insulating layers at preselected locations; applying a third insulating layer over the second insulating layer; and enlarging the upper portion of the vias to define a stepped configuration prior to applying the second metal layer.

Claim 16

An improved method for forming multiple interconnect layers on a semiconductor device, said method including the steps of: (a) defining a first metal layer, having a preselected interconnect pattern, on the device; (b) applying a first insulating layer of the first metal layer; (c) forming vias through the first insulating layer; and (d) defining a second metal layer, having a preselected interconnect pattern, over the first insulating layer; wherein the improvement comprises: planarizing the first insulating layer by applying a planarization layer over the first insulating layer and etching both the planarization layer and the first insulating layer to impart a smoothed profile to the first insulating layer; applying a second insulating layer over the smoothed first insulating layer; forming the vias through both the first and second insulating layers at preselected locations; applying a third insulating layer over the second insulating layer; and enlarging the upper portion of the vias to define a stepped configuration prior to applying the second metal layer.

Claim 17

An improved method as in claim 14, wherein the enlarged portion of the vias extends about half way through the combined thickness of the three insulating layers.

Claim 18

An improved method as in claim 15, wherein the enlarged portion of the vias terminates in the second insulating layer.

Claim 19

An improved method as in claim 14, wherein the metal layers are aluminum, aluminum-copper, aluminum-silicon, or aluminum-silicon-copper.

Claim 20

An improved method as in claim 14, wherein the insulating layers are silicon dioxide or phosphorous-silicon dioxide.

Claim 21

An improved method as in claim 18, wherein the insulating layers are deposited by pyrolysis of silane or silane in the presence of phosphine.

Claim 22

A method as in claim 14, wherein the vias are formed and enlarged by plasma etching.

Claim 23

A method as in claim 14, wherein the planarization layer is photoresist.

Claim 24

A method as in claim 14, wherein the planarization layer and first insulating layer are planarized by plasma etching.

Claim 25

A method as in claim 14, wherein the via etching and planarization etching are performed using the same etchant.

Claim 26

A method as in claim 23, wherein the etchant is selected to have an etch ratio of about 1.6:1.0 (insulating layer:planarization layer).

Claim 27

A method as in claim 17, wherein the first metal layer is underlaid by a titanium-tungsten layer.

Claim 28

A method as in claim 17, wherein the second metal layer is underlaid by a layer which contains titanium.

Claim 29

A method as in claim 17, wherein all metal layers are sandwich layers having a tungsten-titanium layer and an aluminum or aluminum-copper layer.

Claim 30

A method as in claim 24, wherein the etchant has an anisotropic etch ratio of 1 to 2 or more (horizontal etch to vertical etch).