US4415606A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of reworking upper metal in multilayer metal integrated circuits
Assignee: MagnaChip Semiconductor Ltd
•
Filing: 1983-01-10
•
Granted: 1983-11-15
•
Expires: 2003-01-10
Abstract
Abstract A process for reworking the upper level metal layer of an integrated circuit wafer having multiple levels of metal connected by vias through intermediate dielectric layers. In one form, a photoresist masking layer is first formed over the defective upper level metal using an expanded reverse field pattern of the vias. The wafer is then subjected to a metal etch to completely remove the exposed upper level metal while etching into the metal under the photoresist until the etching enters the metal in the via. Thereafter, the residual photoresist is removed. The rework process is concluded with a single chamber operation composed of a sputter etch followed by the deposition of new upper level metal. The concluding chamber sequence ensures the proper via metal surface conditioning for reliable deposition bonding of the new upper level metal deposited thereon.
Inventors
- 👤 Thomas E. Cynkar
- 👤 James G. House
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:17
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H05; H05K; H05K3/00; H05K3/22; H05K3/225; H10P; H10P50/00; H10P50/60; H10P50/66; H10P50/663; H10P50/667; H10W20/062; H05K3/02; H05K3/06; H05K3/061; H05K3/064; H05K3/46; H05K3/4644; Y; Y10; Y10S; Y10S438/00; Y10S438/906
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
108 words
An upper level metal rework process for a multilevel metal integrated circuit wafer having multilevel metal conductors joined by vias through dielectric layers, comprising the steps of: forming a photoresist mask layer over each metal via, said mask having a dimension nominally greater than said via; etching the upper level metal with an etchant that does not materially etch the dielectric, until the etched region of the upper level metal just enters the recessed region of the via; removing the masking photoresist; sputter etching the wafer in an evacuated chamber; and depositing a new layer of upper level metal without exposing the sputter etched wafer to atmospheric ambients.
Claim 2
Dependent Claim
108 words
An upper level metal rework process for a multilevel metal integrated circuit wafer having multilevel metal conductors joined by vias through dielectric layers, comprising the steps of: forming a photoresist mask layer over each metal via, said mask having a dimension nominally greater than said via; etching the upper level metal with an etchant that does not materially etch the dielectric, until the etched region of the upper level metal just enters the recessed region of the via; removing the masking photoresist; sputter etching the wafer in an evacuated chamber; and depositing a new layer of upper level metal without exposing the sputter etched wafer to atmospheric ambients.
Claim 3
Dependent Claim
39 words
The process recited in claim 1, including the additional steps of: etching the wafer briefly with a poly/oxide etchant; and etching the wafer briefly with a premetal etch of buffered hydrofluoric acid; perform before said step of sputter etching.
Claim 4
Dependent Claim
89 words
The process recited in claim 2, wherein: said greater dimension of said photoresist pattern and the thickness of the upper level metal are in a nominal proportion of 2.5:1; said wafer metal is an aluminum alloy with small percentages of copper and silicon; said metal etchant is a composition of phosphoric acid with significantly lesser proportions of acetic acid, nitric acid and DI water; and said poly/oxide etchant is a composition of acetic acid, a significantly lesser proportion of nitric acid, and a relatively small proportion of hydrofluoric acid,
Claim 5
Dependent Claim
62 words
The process recited in claim 3, wherein said step of forming a photoresist comprises the steps of: forming a photolithographic reverse field mask of the via, with each peripheral dimension of the via pattern increased by an amount in the range of 2.5 times the upper level metal thickness; coating the wafer with photoresist material; and exposing and developing the photoresist material.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-14 | 1987-05-16 | 1987-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-14 | 1991-05-16 | 1991-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-14 | 1995-05-16 | 1995-11-15 | $7700.00 | Window Closed / Lapsed |