US3976524A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Planarization of integrated circuit surfaces through selective photoresist masking
Assignee: International Business Machines Corp
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Filing: 1974-06-17
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Granted: 1976-08-24
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Expires: 1994-06-17
Abstract
Abstract An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with the pattern of unelevated areas, the photoresist pattern having narrower lateral dimensions than said elevated pattern whereby registration is facilitated, flowing the photoresist pattern to laterally expand the photoresist to cover and thereby mask the unelevated areas, and etching to lower the elevated areas which remain uncovered by the photoresist.
Inventors
- 👤 Bai-Cwo Feng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:02
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; G; G03; G03F; G03F7/00; G03F7/16; H10P; H10P14/00; H10P14/60; H10P14/61; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10P95/066; H10P95/08; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17; H10W74/43; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/085; Y10S148/105; Y10S148/131
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
77 words
A method of photoresist masking comprising forming, on a substrate surface having a pattern of elevated areas and a complementary pattern of unelevated areas, a photoresist pattern in registration with said pattern of unelevated areas, said photoresist pattern having narrower lateral dimensions than said unelevated pattern whereby said registration is facilitated, and flowing said photoresist pattern by treating said photoresist with a photoresist solvent to laterally expand the photoresist to cover and thereby mask said unelevated areas.
Claim 2
Independent Claim
77 words
A method of photoresist masking comprising forming, on a substrate surface having a pattern of elevated areas and a complementary pattern of unelevated areas, a photoresist pattern in registration with said pattern of unelevated areas, said photoresist pattern having narrower lateral dimensions than said unelevated pattern whereby said registration is facilitated, and flowing said photoresist pattern by treating said photoresist with a photoresist solvent to laterally expand the photoresist to cover and thereby mask said unelevated areas.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein said treatment is with the vapor of said solvent.
Claim 4
Dependent Claim
16 words
The method of claim 1 including the further step of etching to lower said elevated areas.
Claim 5
Dependent Claim
15 words
The method of claim 3 wherein said etching step is carried out by sputter etching.
Claim 6
Dependent Claim
13 words
The method of claim 3 wherein said etching is with a chemical etchant.
Claim 7
Dependent Claim
16 words
The method of claim 2 including the further step of etching to lower said elevated areas.
Claim 8
Dependent Claim
15 words
The method of claim 6 wherein said etching step is carried out by sputter etching.
Claim 9
Dependent Claim
13 words
The method of claim 5 wherein said etching is with a chemical etchant.
Claim 10
Dependent Claim
14 words
The method of claim 8 wherein said substrate surface is an electrically insulative material.
Claim 11
Dependent Claim
22 words
The method of claim 9 wherein said substrate comprises a layer of said electrically insulative material covering an integrated semiconductor circuit member.
Claim 12
Dependent Claim
23 words
The method of claim 3 wherein said elevated areas are lowered substantially to the level of said unelevated areas, thereby planarizing the surface.
Claim 13
Dependent Claim
23 words
The method of claim 9 wherein said elevated areas are lowered substantially to the level of said unelevated areas, thereby planarizing the surface.
Claim 14
Dependent Claim
38 words
The method of claim 10 wherein said integrated circuit member has formed on the surface thereof a conductive raised line pattern corresponding to and in registration with the pattern of elevated areas in said covering electrically insulative layer.
Claim 15
Dependent Claim
28 words
The method of claim 13 wherein said elevated areas are lowered substantially to the level of said unelevated areas, thereby planarizing the surface of the electrically insulative layer.
Claim 16
Dependent Claim
32 words
The method of claim 14 including the further step of etching at least one via hole, through a lowered elevated area of said insulative layer, extending to an underlying raised conductive line.
Claim 17
Independent Claim
142 words
A method for forming a dielectrically isolated integrated semiconductor circuit comprising forming in a semiconductor substrate a pattern of trenches extending from a surface of said substrate, said trench pattern laterally enclosing respectively a plurality of pockets of said semiconductor substrate, forming over said semiconductor substrate a layer of electrically insulative material whereby said layer has a pattern of depressed areas corresponding to and filling said trench pattern and a complementary pattern of undepressed areas, forming in said depressed areas a photoresist pattern in registration with said depressed area pattern, said photoresist pattern having narrower lateral dimensions than said depressed area pattern whereby registration is facilitated, flowing said photoresist pattern by treating said photoresist with a photoresist solvent to laterally expand the photoresist to cover and thereby mask said depressed areas, and etching to lower said undepressed areas of said insulative layer.
Claim 18
Independent Claim
142 words
A method for forming a dielectrically isolated integrated semiconductor circuit comprising forming in a semiconductor substrate a pattern of trenches extending from a surface of said substrate, said trench pattern laterally enclosing respectively a plurality of pockets of said semiconductor substrate, forming over said semiconductor substrate a layer of electrically insulative material whereby said layer has a pattern of depressed areas corresponding to and filling said trench pattern and a complementary pattern of undepressed areas, forming in said depressed areas a photoresist pattern in registration with said depressed area pattern, said photoresist pattern having narrower lateral dimensions than said depressed area pattern whereby registration is facilitated, flowing said photoresist pattern by treating said photoresist with a photoresist solvent to laterally expand the photoresist to cover and thereby mask said depressed areas, and etching to lower said undepressed areas of said insulative layer.
Claim 19
Dependent Claim
15 words
The method of claim 16 wherein said treatment is with the vapor of said solvent.
Claim 20
Dependent Claim
15 words
The method of claim 17 wherein said etching step is carried out by sputter etching.
Claim 21
Dependent Claim
13 words
The method of claim 17 wherein said etching is with a chemical etchant.
Claim 22
Independent Claim
341 words
A method for forming a dielectrically isolated integrated semiconductor circuit comprising masking a semiconductor substrate surface with a first layer of electrically insulative material having a pattern of openings corresponding to trenches to be etched in the substrate. etching with an etchant which preferentially etches the semiconductor substrate material to form a pattern of trenches in said substrate extending from said surface, said etching being conducted for a time sufficient so that said trenches undercut said insulative layer adjacent said openings, depositing a second layer of electrically insulative material over said first layer and under the undercut portions of said first insulative layer, and over the substrate exposed in said trenches, said first insulative material being more etchable than said second insulative material in selected etchants, depositing over said second insulative layer, a third layer of electrically insulative material whereby said third layer has a pattern of depressed areas corresponding to and filling said trench pattern and a complementary pattern of undepressed areas, said material of said third layer having a different etchability than said second insulative material in selected etchants, forming in said depressed areas a photoresist pattern in registration with said depressed area pattern, said photoresist pattern having narrower lateral dimensions than said depressed area pattern whereby registration is facilitated, flowing said photoresist pattern to laterally expand the photoresist to cover and thereby mask said depressed areas, etching to lower said undepressed areas of said third layer and to remove said undepressed areas of said third layer to expose the portions of the second insulative layer underlying said undepressed areas, etching with an etchant which preferentially etches the material of the second layer to remove the exposed portions of said second layer, thereby exposing the underlying portions of the first layer, and removing selected portions of said exposed first layer from said substrate surface adjacent said trenches with an etchant which preferentially etches said first layer, said second layer under the undercut portions of said first layer protecting the substrate adjacent said trenches from lateral exposure during the etching.
Claim 23
Independent Claim
341 words
A method for forming a dielectrically isolated integrated semiconductor circuit comprising masking a semiconductor substrate surface with a first layer of electrically insulative material having a pattern of openings corresponding to trenches to be etched in the substrate. etching with an etchant which preferentially etches the semiconductor substrate material to form a pattern of trenches in said substrate extending from said surface, said etching being conducted for a time sufficient so that said trenches undercut said insulative layer adjacent said openings, depositing a second layer of electrically insulative material over said first layer and under the undercut portions of said first insulative layer, and over the substrate exposed in said trenches, said first insulative material being more etchable than said second insulative material in selected etchants, depositing over said second insulative layer, a third layer of electrically insulative material whereby said third layer has a pattern of depressed areas corresponding to and filling said trench pattern and a complementary pattern of undepressed areas, said material of said third layer having a different etchability than said second insulative material in selected etchants, forming in said depressed areas a photoresist pattern in registration with said depressed area pattern, said photoresist pattern having narrower lateral dimensions than said depressed area pattern whereby registration is facilitated, flowing said photoresist pattern to laterally expand the photoresist to cover and thereby mask said depressed areas, etching to lower said undepressed areas of said third layer and to remove said undepressed areas of said third layer to expose the portions of the second insulative layer underlying said undepressed areas, etching with an etchant which preferentially etches the material of the second layer to remove the exposed portions of said second layer, thereby exposing the underlying portions of the first layer, and removing selected portions of said exposed first layer from said substrate surface adjacent said trenches with an etchant which preferentially etches said first layer, said second layer under the undercut portions of said first layer protecting the substrate adjacent said trenches from lateral exposure during the etching.
Claim 24
Dependent Claim
19 words
The method of claim 2 wherein said first layer comprises silicon dioxide and said second layer comprises silicon oxynitride.
Claim 25
Dependent Claim
12 words
The method of claim 21 wherein said third layer comprises silicon dioxide.
Claim 26
Dependent Claim
32 words
The method of claim 22 wherein said first layer is a composite layer comprising a silicon dioxide bottom layer in contact with the substrate surface and a top layer of silicon nitride.
Claim 27
Dependent Claim
19 words
The method of claim 20 wherein said first layer comprises silicon dioxide and said second layer comprises silicon nitride.
Claim 28
Dependent Claim
12 words
The method of claim 24 wherein said third layer comprises silicon dioxide.
Claim 29
Independent Claim
348 words
A method for forming a dielectrically isolated integrated semiconductor circuit comprising masking a semiconductor substrate surface with a first layer of electrically insulative material having a pattern of openings corresponding to trenches to be etched in the substrate, etching with an etchant which preferentially etches the semiconductor substrate material to form a pattern of trenches in said substrate extending from said surface, said etching being conducted for a time sufficient so that said trenches undercut said insulative layer adjacent said openings, depositing a second layer of electrically insulative material over said first layer and under the undercut portions of said first insulative layer and over the substrate exposed in said trenches, said first insulative material being more etchable than said second insulative material in selected etchants, depositing over said second insulative layer, a third layer of electrically insulative material whereby said third layer has a pattern of depressed areas corresponding to and filling said trench pattern and a complementary pattern of undepressed areas, said material of said third layer having a different etchability than said second insulative material in selected etchants, forming in said depressed areas a photoresist pattern in registration with said depressed area pattern, said photoresist pattern having narrower lateral dimensions than said depressed area pattern whereby registration is facilitated, flowing said photoresist pattern to laterally expand the photoresist to cover and thereby mask said depressed areas, etching to lower said undepressed areas of said third layer to the level of said depressed areas and to remove said undepressed areas of said third layer to expose the portions of the second insulative layer underlying said undepressed area, etching with an etchant which preferentially etches the material of the second layer to remove the exposed portions of said second layer, thereby exposing the underlying portions of the first layer, and removing selected portions of said exposed first layer from said substrate surface adjacent said trenches with an etchant which preferentially etches said first layer, said second layer under the undercut portions of said first layer protecting the substrate adjacent said trenches from lateral exposure during the etching.
Claim 30
Independent Claim
348 words
A method for forming a dielectrically isolated integrated semiconductor circuit comprising masking a semiconductor substrate surface with a first layer of electrically insulative material having a pattern of openings corresponding to trenches to be etched in the substrate, etching with an etchant which preferentially etches the semiconductor substrate material to form a pattern of trenches in said substrate extending from said surface, said etching being conducted for a time sufficient so that said trenches undercut said insulative layer adjacent said openings, depositing a second layer of electrically insulative material over said first layer and under the undercut portions of said first insulative layer and over the substrate exposed in said trenches, said first insulative material being more etchable than said second insulative material in selected etchants, depositing over said second insulative layer, a third layer of electrically insulative material whereby said third layer has a pattern of depressed areas corresponding to and filling said trench pattern and a complementary pattern of undepressed areas, said material of said third layer having a different etchability than said second insulative material in selected etchants, forming in said depressed areas a photoresist pattern in registration with said depressed area pattern, said photoresist pattern having narrower lateral dimensions than said depressed area pattern whereby registration is facilitated, flowing said photoresist pattern to laterally expand the photoresist to cover and thereby mask said depressed areas, etching to lower said undepressed areas of said third layer to the level of said depressed areas and to remove said undepressed areas of said third layer to expose the portions of the second insulative layer underlying said undepressed area, etching with an etchant which preferentially etches the material of the second layer to remove the exposed portions of said second layer, thereby exposing the underlying portions of the first layer, and removing selected portions of said exposed first layer from said substrate surface adjacent said trenches with an etchant which preferentially etches said first layer, said second layer under the undercut portions of said first layer protecting the substrate adjacent said trenches from lateral exposure during the etching.
Claim 31
Dependent Claim
19 words
The method of claim 26 wherein said first layer comprises silicon dioxide and said second layer comprises silicon oxynitride.
Claim 32
Dependent Claim
12 words
The method of claim 27 wherein said third layer comprises silicon dioxide.
Claim 33
Dependent Claim
32 words
The method of claim 28 wherein said first layer is a composite layer comprising a silicon dioxide bottom layer in contact with the substrate surface and a top layer of silicon nitride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-24 | 1980-02-23 | 1980-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-24 | 1984-02-23 | 1984-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-24 | 1988-02-23 | 1988-08-24 | $7700.00 | Window Closed / Lapsed |