Patent US6873539B1 successfully refreshed from Google Patents.
US6873539B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Micron Technology Inc
•
Filing: 2003-12-04
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Granted: 2005-03-29
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Expires: 2023-12-04
Abstract
Abstract A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.
Inventors
- 👤 Pierre Fazan
- 👤 Serguei Okhonin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:35
CPC Classifications
H; H10; H10B; H10B12/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/56; G11C11/5621; H10B12/01; H10B12/20; H10D; H10D30/00; H10D30/60; H10D30/711; H10D86/00; H10D86/01; H10D86/201; G11C2211/00; G11C2211/401; G11C2211/4016; Y; Y10; Y10S; Y10S257/00; Y10S257/905; Y10S257/907; Y10S438/00; Y10S438/982
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
169 words
A semiconductor memory array comprising: a plurality of memory cells arranged in a matrix of rows and columns, the plurality of memory cells includes a first memory cell and a second memory cell, wherein the first and second memory cells each includes at least a transistor to constitute the memory cell and wherein the transistor includes: a source region; a drain region; a body region disposed between and adjacent to the source region and the drain region, wherein the body region is an electrically floating state; and a gate disposed over the body region; wherein each memory cell includes: a first data state representative of a first charge in the body region; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the gate of the transistor of the first memory cell and the gate of the transistor of the second memory cell are connected.
Claim 2
Dependent Claim
169 words
A semiconductor memory array comprising: a plurality of memory cells arranged in a matrix of rows and columns, the plurality of memory cells includes a first memory cell and a second memory cell, wherein the first and second memory cells each includes at least a transistor to constitute the memory cell and wherein the transistor includes: a source region; a drain region; a body region disposed between and adjacent to the source region and the drain region, wherein the body region is an electrically floating state; and a gate disposed over the body region; wherein each memory cell includes: a first data state representative of a first charge in the body region; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the gate of the transistor of the first memory cell and the gate of the transistor of the second memory cell are connected.
Claim 3
Dependent Claim
192 words
The memory array of claim 1 wherein: the plurality of memory cells further includes a third memory cell and a fourth memory cell, wherein the third and fourth memory cells each includes at least a transistor to constitute the memory cell and wherein the transistor includes: a source region; a drain region; a body region disposed between and adjacent to the source region and the drain region, wherein the body region is an electrically floating state; and a gate disposed over the body region; wherein each memory cell includes: a first data state representative of a first charge in the body region; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the source region of the transistor of the first memory cell and the source region of the transistor of the third memory cell are the same region and wherein the drain region of the transistor of the first memory cell and the drain region of the transistor of the fourth memory cell are the same region.
Claim 4
Dependent Claim
30 words
The memory array of claim 1 wherein the first charge is comprised of an accumulation of majority carriers in the body region of the transistor of the first memory cell.
Claim 5
Dependent Claim
38 words
The memory array of claim 3 wherein the majority carriers accumulate in a portion of the body region that is adjacent to the source region of the transistor of each memory cell of the plurality of memory cells.
Claim 6
Dependent Claim
62 words
The memory array of claim 1 further including a control unit, coupled to the gate and the drain region of the first memory cell, to provide control signals to the first memory cell, wherein the first memory cell, in response to a first write control signals, stores the first charge in the body region of the transistor of the first memory cell.
Claim 7
Dependent Claim
81 words
The memory array of claim 1 further including a control unit, coupled to the gate and the drain region of the first memory cell, to provide control signals to the first memory cell, wherein the first memory cell, in response to a second write control signals, stores the second charge in the body region of the transistor of the first memory cell by removing charge from the body region of the transistor of the first memory cell through its source region.
Claim 8
Dependent Claim
44 words
The memory array of claim 6 wherein the control unit applies positive voltages to the drain region and gate of the transistor of the first memory cell to provide the second charge in the body region of the transistor of the first memory cell.
Claim 9
Dependent Claim
92 words
The memory array of claim 7 wherein the control unit is coupled to the gate, drain region and source region of the transistor of the second memory cell and applies positive voltages to the drain region and gate of the transistor of the first memory cell to provide the second charge in the body region of the transistor of the first memory cell and applies a first voltage to the drain and source regions of the transistor of the second memory cell to maintain the data state of the second memory cell.
Claim 10
Dependent Claim
12 words
The memory array of claim 8 wherein the first voltage is ground.
Claim 11
Dependent Claim
213 words
A semiconductor memory array comprising: a plurality of memory cells arranged in a matrix of rows and columns, the plurality of memory cell includes a first memory cell and a second memory cell, wherein the first and second memory cells each includes at least a transistor to constitute the memory cell and wherein the transistor includes: a source region having impurities to provide a first conductivity type; a drain region having impurities to provide the first conductivity type, a body region disposed between and adjacent to the source region and the drain region wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different than the first conductivity type; a gate disposed over the body region; wherein the memory cell includes: a first data state representative of a first charge in the body region wherein the first charge is substantially provided by impact ionization; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the gate of the transistor of the first memory cell and the gate of the transistor of the second memory cell are connected.
Claim 12
Dependent Claim
213 words
A semiconductor memory array comprising: a plurality of memory cells arranged in a matrix of rows and columns, the plurality of memory cell includes a first memory cell and a second memory cell, wherein the first and second memory cells each includes at least a transistor to constitute the memory cell and wherein the transistor includes: a source region having impurities to provide a first conductivity type; a drain region having impurities to provide the first conductivity type, a body region disposed between and adjacent to the source region and the drain region wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different than the first conductivity type; a gate disposed over the body region; wherein the memory cell includes: a first data state representative of a first charge in the body region wherein the first charge is substantially provided by impact ionization; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the gate of the transistor of the first memory cell and the gate of the transistor of the second memory cell are connected.
Claim 13
Dependent Claim
199 words
The memory array of claim 10 wherein: the plurality of memory cells further includes a third memory cell wherein the third memory cell includes at least a transistor to constitute the memory cell wherein the transistor includes: a source region having impurities to provide the first conductivity type; a drain region having impurities to provide the first conductivity type, a body region disposed between and adjacent to the source region and the drain region wherein the body region is electrically floating and includes impurities to provide the second conductivity type wherein the second conductivity type is different than the first conductivity type; a gate disposed over the body region; and wherein the memory cell includes: a first data state representative of a first charge in the body region wherein the first charge is substantially provided by impact ionization; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the source region of the transistor of the first memory cell and the source region of the transistor of the third memory cell are the same region.
Claim 14
Dependent Claim
198 words
The memory array of claim 10 wherein: the plurality of memory cells further includes a fourth memory cell wherein the fourth memory cell includes at least a transistor to constitute the memory cell wherein the transistor includes: a source region having impurities to provide the first conductivity type; a drain region having impurities to provide the first conductivity type, a body region disposed between and adjacent to the source region and the drain region wherein the body region is electrically floating and includes impurities to provide the second conductivity type wherein the second conductivity type is different than the first conductivity type; a gate disposed over the body region, wherein the memory cell includes: a first data state representative of a first charge in the body region wherein the first charge is substantially provided by impact ionization; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the drain region of the transistor of the first memory cell and the drain region of the transistor of the fourth memory cell are the same region.
Claim 15
Dependent Claim
30 words
The memory array of claim 12 wherein the first charge is comprised of an accumulation of majority carriers in the body region of the transistor of the first memory cell.
Claim 16
Dependent Claim
38 words
The memory array of claim 13 wherein the majority carriers accumulate in a portion of the body region that is adjacent to the source region of the transistor of each memory cell of the plurality of memory cells.
Claim 17
Dependent Claim
65 words
The memory array of claim 12 further including a control unit, coupled to the gate and the drain region of the transistor of the first memory cell, to provide control signals to the first memory cell, wherein the first memory cell, in response to a first write control signals, stores the first charge in the body region of the transistor of the first memory cell.
Claim 18
Dependent Claim
83 words
The memory array of claim 12 further including a control unit, coupled to the gate and the drain region of the transistor of the first memory cell, to provide control signals to the first memory cell, wherein the first memory cell, in response to second write control signals, stores the second charge in the body region of the transistor of the first memory cell by removing charge from the body region of the transistor of the first memory cell through its source region.
Claim 19
Dependent Claim
44 words
The memory array of claim 16 wherein the control unit applies positive voltages to the drain region and gate of the transistor of the first memory cell to provide the second charge in the body region of the transistor of the first memory cell.
Claim 20
Dependent Claim
92 words
The memory array of claim 17 wherein the control unit is coupled to the gate, drain region and source region of the transistor of the second memory cell and applies positive voltages to the drain region and gate of the transistor of the first memory cell to provide the second charge in the body region of the transistor of the first memory cell and applies a first voltage to the drain and source regions of the transistor of the second memory cell to maintain the data state of the second memory cell.
Claim 21
Dependent Claim
12 words
The memory array of claim 18 wherein the first voltage is ground.
Claim 22
Dependent Claim
238 words
A semiconductor memory array, disposed in or on a semiconductor layer which resides on or above an insulating layer of a substrate, the semiconductor memory array comprising: a plurality of memory cells, including a first memory cell and a second memory cell, arranged in a matrix of rows and columns and disposed in or on the semiconductor layer, wherein the first and second memory cells each includes at least a transistor to constitute the memory cell and wherein the transistor includes: a source region having impurities to provide a first conductivity type; a drain region having impurities to provide the first conductivity type, a body region disposed between and adjacent to the source region, the drain region and the insulating layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different than the first conductivity type; a gate spaced apart from, and capacitively coupled to, the body region; wherein the memory cell includes: a first data state representative of a first charge in the body; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the gate of the transistor of the first memory cell and the gate of the transistor of the second memory cell are connected.
Claim 23
Dependent Claim
238 words
A semiconductor memory array, disposed in or on a semiconductor layer which resides on or above an insulating layer of a substrate, the semiconductor memory array comprising: a plurality of memory cells, including a first memory cell and a second memory cell, arranged in a matrix of rows and columns and disposed in or on the semiconductor layer, wherein the first and second memory cells each includes at least a transistor to constitute the memory cell and wherein the transistor includes: a source region having impurities to provide a first conductivity type; a drain region having impurities to provide the first conductivity type, a body region disposed between and adjacent to the source region, the drain region and the insulating layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different than the first conductivity type; a gate spaced apart from, and capacitively coupled to, the body region; wherein the memory cell includes: a first data state representative of a first charge in the body; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the gate of the transistor of the first memory cell and the gate of the transistor of the second memory cell are connected.
Claim 24
Dependent Claim
193 words
The memory array of claim 20 wherein: the plurality of memory cells further includes a third memory cell wherein the third memory cell includes at least a transistor to constitute the memory cell wherein the transistor includes: a source region having impurities to provide the first conductivity type; a drain region having impurities to provide the first conductivity type; a body region disposed between and adjacent to the source region and the drain region wherein the body region is electrically floating and includes impurities to provide the second conductivity type wherein the second conductivity type is different than the first conductivity type; a gate spaced apart from, and capacitively coupled to, the body region; and wherein the memory cell includes: a first data state representative of a first charge in the body; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the source region of the transistor of the first memory cell and the source region of the transistor of the third memory cell are the same region.
Claim 25
Dependent Claim
193 words
The memory array of claim 21 wherein: the plurality of memory cells further includes a fourth memory cell wherein the fourth memory cell includes at least a transistor to constitute the memory cell wherein the transistor includes: a source region having impurities to provide the first conductivity type; a drain region having impurities to provide the first conductivity type; a body region disposed between and adjacent to the source region and the drain region wherein the body region is electrically floating and includes impurities to provide the second conductivity type wherein the second conductivity type is different than the first conductivity type; a gate spaced apart from, and capacitively coupled to, the body region; and wherein the memory cell includes: a first data state representative of a first charge in the body; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the drain region of the transistor of the first memory cell and the drain region of the transistor of the fourth memory cell are the same region.
Claim 26
Dependent Claim
43 words
The memory array of claim 20 wherein the second charge is provided in the body of the transistor of the first memory cell in response to a first positive voltage applied to the drain region of the transistor of the first memory cell.
Claim 27
Dependent Claim
61 words
The memory array of claim 23 wherein the second charge is stored in the body region of the transistor of the first memory cell in response to removing the first positive voltage from the drain region of the transistor of the first memory cell before removing a second positive voltage from the gate of the transistor of the first memory cell.
Claim 28
Dependent Claim
41 words
The memory array of claim 24 wherein, in response to the first and second positive voltages, the first memory cell includes a forward bias current between the body region and the source region of the transistor of the first memory cell.
Claim 29
Dependent Claim
65 words
The memory array of claim 25 wherein the second charge is stored in the body region of the transistor of the first memory cell in response to removing the first positive voltage from the drain region of the transistor of the first memory cell and wherein the source regions of the transistors of the first and second memory cells are connected to a fixed voltage.
Claim 30
Dependent Claim
30 words
The memory array of claim 20 wherein the first charge is comprised of an accumulation of majority carriers in the body region of the transistor of the first memory cell.
Claim 31
Dependent Claim
38 words
The memory array of claim 27 wherein the majority carriers accumulate in a portion of the body region that is adjacent to the source region of the transistor of each memory cell of the plurality of memory cells.
Claim 32
Dependent Claim
65 words
The memory array of claim 20 further including a control unit, coupled to the gate and the drain region of the transistor of the first memory cell, to provide control signals to the first memory cell, wherein the first memory cell, in response to a first write control signals, stores the first charge in the body region of the transistor of the first memory cell.
Claim 33
Dependent Claim
82 words
The memory array of claim 20 further including a control unit, coupled to the gate and the drain region of the transistor of the first memory cell, to provide control signals to the first memory cell, wherein the first memory cell, in response to second write control signals, stores the second charge in the body region of the transistor of the first memory by removing charge from the body region of the transistor of the first memory cell through its source region.
Claim 34
Dependent Claim
44 words
The memory array of claim 30 wherein the control unit applies positive voltages to the drain region and gate of the transistor of the first memory cell to provide the second charge in the body region of the transistor of the first memory cell.
Claim 35
Dependent Claim
73 words
The memory array of claim 31 wherein the control unit applies positive voltages to the drain region and gate of the transistor of the first memory cell to provide the second charge in the body region of the transistor of the first memory cell and applies a first voltage to the drain and source regions of the transistor of the second memory cell to maintain the data state of the second memory cell.
Claim 36
Dependent Claim
12 words
The memory array of claim 32 wherein the first voltage is ground.
References Cited (Backward Citations)
US3439214A
Cited
US4032947A
Cited
GB1414228A
Cited
FR2197494A5
Cited
US3997799A
Cited
US4298962A
Cited
EP0030856B1
Cited
EP0202515B1
Cited
EP0175378B1
Cited
US4791610A
Cited
EP0207619B1
Cited
EP0245515B1
Cited
JPS62272561A
Cited
EP0253631B1
Cited
EP0300157B1
Cited
US4979014A
Cited
EP0333426B1
Cited
EP0350057B1
Cited
EP0354348A2
Cited
US5164805A
Cited
US5144390A
Cited
US5258635A
Cited
EP0359551B1
Cited
EP0362961A1
Cited
EP0362961B1
Cited
EP0366882B1
Cited
JPH02294076A
Cited
JPH03171768A
Cited
EP0689252B1
Cited
US5388068A
Cited
EP0465961B1
Cited
EP0510607B1
Cited
EP0513923B1
Cited
EP0537677B1
Cited
EP0564204A2
Cited
EP0836194B1
Cited
US5466625A
Cited
US5528062A
Cited
EP0579566A2
Cited
EP0599388B1
Cited
EP0599506A1
Cited
EP0971360A1
Cited
EP0601590B1
Cited
US5968840A
Cited
EP0606758B1
Cited
US5631186A
Cited
US5939745A
Cited
EP1204146A1
Cited
EP1204147A1
Cited
EP0642173A1
Cited
EP0933820A1
Cited
EP0642173B1
Cited
EP0844671B1
Cited
US5608250A
Cited
EP0731972B1
Cited
US5448513A
Cited
US6121077A
Cited
US6300649B1
Cited
US5489792A
Cited
US5982003A
Cited
US5446299A
Cited
EP0682370B1
Cited
EP0694977A3
Cited
US6018172A
Cited
US5627092A
Cited
US6384445B1
Cited
US5593912A
Cited
US5696718A
Cited
EP0725402B1
Cited
US6292424B1
Cited
US6351426B1
Cited
EP0726601B1
Cited
US5740099A
Cited
JPH08213624A
Cited
EP0727822B1
Cited
EP1209747A2
Cited
EP0727820A1
Cited
US6252281B1
Cited
JPH08274277A
Cited
US5568356A
Cited
EP0739097A2
Cited
US5606188A
Cited
EP0744772B1
Cited
US5780906A
Cited
JPH0946688A
Cited
JPH0982912A
Cited
US5977578A
Cited
EP0788165A2
Cited
US6081443A
Cited
US5877978A
Cited
US5936265A
Cited
EP0951072A1
Cited
EP0801427A3
Cited
US6424016B1
Cited
US20020180069A1
Cited
US5960265A
Cited
US5886376A
Cited
US5778243A
Cited
US5811283A
Cited
US5886385A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2008-03-28 | 2008-09-27 | 2009-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-03-28 | 2012-09-27 | 2013-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-03-28 | 2016-09-27 | 2017-03-29 | $7700.00 | Window Closed / Lapsed |