MOS transistor

Claim 2

An MOS transistor comprising: a semiconductor substrate having a projection and a first conductivity type on a major surface thereof, said projection having an upper surface and opposite side surfaces substantially perpendicular to said upper surface; a gate insulating film formed on said upper and side surfaces of said projection; source and drain regions formed on the upper surface of said projection and separated from each other while sandwiching said gate insulating film, said source and drain regions having a second conductivity type; a gate electrode formed on said gate insulating film and having an upper portion opposing the upper surface of said projection, a pair of opposite side portions opposing the pair of side surfaces of said projection, and corner portions located between the side and upper portions; and means for applying a voltage to said gate electrode to form adjacent said upper portion a depletion layer extending a first depth into said projection from said upper portion and to form depletion layers extending from said corner portions and connected to each other in said projection at a second depth greater than said first depth.

Claim 3

A transistor according to claim 1, wherein the second portion of said gate electrode comprises an end portion located at an intermediate level of the side surface of said projection.

Claim 4

A transistor according to claim 2, further comprising an isolation layer formed on said substrate, located between said substrate and the second portion of said gate electrode.

Claim 5

An MOS transistor comprising: a substrate having a main surface; a projection formed on the main surface of said substrate and having an upper surface and a pair of opposite side surfaces; a gate insulating film having an upper portion located on the upper surface of said projection and a pair of side portions extending from the upper portion and located on the side surfaces of said projection; source and drain regions located in said projection to sandwich said gate insulating film and to be exposed on the upper surface of said projection; a gate electrode, having first and second portions respectively formed on the upper and side portions of said gate insulating film, for generating a depletion layer extending closer to said substrate than a depletion layer generated by only the first portion, in the portion of the projection facing the first portion; and a polysilicon layer formed on said substrate, located between said substrate and the second portion of said gate electrode, and electrically insulated from said gate electrode; wherein the second portion of said gate electrode comprises an end portion located at an intermediate level of the side surface of said projection, and the side and upper surface of the projection intersect at substantially right angles.

Claim 6

An MOS transistor comprising: a substrate having a main surface; a projection formed on the main surface of said substrate and having an upper surface and a pair of opposite side surfaces; a gate insulating film having an upper portion located on the upper surface of said projection and a pair of side portions extending from the upper portion and located on the side surfaces of said projection; source and drain regions located in said projection to sandwich said gate insulating film and to be exposed on the upper surface of said projection; a gate electrode, having first and second portions respectively formed on the upper and side portions of said gate insulating film, for generating a depletion layer extending closer to said substrate than a depletion layer generated by only the first portion, in the portion of the projection facing the first portion; and a polysilicon layer formed on said substrate, located between said substrate and the second portion of said gate electrode, and electrically insulated from said gate electrode; wherein the second portion of said gate electrode comprises an end portion located at an intermediate level of the side surface of said projection, and the side and upper surface of the projection intersect at substantially right angles.

Claim 7

A transistor according to claim 4, wherein the side surfaces of said projection extend parallel to each other.

Claim 8

A transistor according to claim 5, wherein the side surfaces of said projection are separated from each other at a maximum distance of 0.8 μm.

Claim 9

A transistor according to claim 6, wherein said gate electrode comprises another side portion extending from the side portion thereof to be substantially parallel to the major surface of said semiconductor substrate, and an insulating film, located between said another side portion and the major surface of said semiconductor substrate, for electrically insulating the conductive layer from said another side portion.

Claim 10

An MOS transistor comprising: a substrate having a main surface; a projection formed on the main surface of said substrate and having an upper surface and a pair of opposite side surfaces; a gate insulating film having an upper portion located on the upper surface of said projection and a pair of side portions extending from the upper portion and located on the side surfaces of said projection; source and drain regions located in said projection to sandwich said gate insulating film and to be exposed on the upper surface of said projection; a gate electrode, having first and second portions respectively formed on the upper and side portions of said gate insulating film, for generating a depletion layer extending closer to said substrate than a depletion layer generated by only the first portion, in the portion of the projection facing the first portion; and an isolation layer formed on said substrate, located between said substrate and the second portion of said gate electrode; wherein the second portion of said gate electrode comprises an end portion located at an intermediate level of the side surface of said projection, and said isolation layer includes a thin insulating layer and a thick layer which are laminated with each other, the thin layer provided between the end portion of the second portion of the gate electrode and the thick layer to electrically insulate the thick layer from the gate electrode.

Claim 11

An MOS transistor comprising: a substrate having a main surface; a projection formed on the main surface of said substrate and having an upper surface and a pair of opposite side surfaces; a gate insulating film having an upper portion located on the upper surface of said projection and a pair of side portions extending from the upper portion and located on the side surfaces of said projection; source and drain regions located in said projection to sandwich said gate insulating film and to be exposed on the upper surface of said projection; a gate electrode, having first and second portions respectively formed on the upper and side portions of said gate insulating film, for generating a depletion layer extending closer to said substrate than a depletion layer generated by only the first portion, in the portion of the projection facing the first portion; and an isolation layer formed on said substrate, located between said substrate and the second portion of said gate electrode; wherein the second portion of said gate electrode comprises an end portion located at an intermediate level of the side surface of said projection, and said isolation layer includes a thin insulating layer and a thick layer which are laminated with each other, the thin layer provided between the end portion of the second portion of the gate electrode and the thick layer to electrically insulate the thick layer from the gate electrode.

Claim 12

A transistor according to claim 8, wherein said isolation layer includes another thin insulating layer between the thick layer and the substrate.

Claim 13

A transistor according to claim 9, wherein said thick layer is made of insulating or conductive material.

Claim 14

A transistor according to claim 10, wherein said thick layer includes a polysilicon layer.