EP0726601B1
Expired / Lapsed
EP
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Semiconductor memory device having a peripheral circuit and an interface circuit located on a bulk region and memory cells located on a semiconductor-on-insulator region
Assignee: NEC Corp
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Filing: 1996-02-07
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Granted: 2001-09-19
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Expires: 2016-02-07
Abstract
No abstract record available.
Inventors
- 👤 Takaho Tanigawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:35
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10D; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
141 words
A semiconductor memory device provided on a semiconductor substrate (30; 50) including a bulk region (30b; 50b) and a further region (30a; 50a) having an insulating layer (30c) isolating a first semiconductor layer (30d; 50c) from an underlying second semiconductor layer (30e), comprising: a memory cell array (31; 51) located on said first semiconductor layer (30d; 50c) in said further region (30a; 50a) for storing pieces of data information; an interface circuit (33; 53) located on said bulk region (30b; 50b) for transferring said pieces of data information to an external device; and a peripheral circuit (32; 52) electrically coupled between said memory cell array (31; 51) and said interface circuit (33; 53) for selectively transferring said pieces of data information therebetween, wherein said peripheral circuit (32; 52) has first logic circuits (32a/32b/32c/32d/32e; 52b) located on said bulk region (30b; 50b).
Claim 2
Dependent Claim
29 words
The semiconductor memory device as set forth in claim 1, in which said first semiconductor layer (30d) has a thickness in the range between 10 nanometres to 100 nanometres.
Claim 3
Dependent Claim
28 words
The semiconductor memory device as set forth in claim 1, in which said memory cell array (31) is formed by a plurality of dynamic random access memory cells.
Claim 4
Dependent Claim
32 words
The semiconductor memory device as set forth in claim 1, in which said first logic circuits include address decoders (32a/32b), selectors (32b), controllers for an addressing system (32c/32d) and sense amplifiers (32e).
Claim 5
Dependent Claim
69 words
The semiconductor memory device as set forth in claim 1, in which said first semiconductor layer (50c) has a thin portion (50d) having a thickness in the range between 10 nanometres and 100 nanometres and a thick portion (50e) having a thickness in the range between 100 nanometres and 150 nanometres, and said memory cell array (51) is located on the thin portion (50d) in the further region (50a).
Claim 6
Dependent Claim
33 words
The semiconductor memory device as set forth in claim 5, in which said peripheral circuit (52) further has second logic circuits (52a) fabricated on said thick portion (50e) in said further region (50a).
Claim 7
Dependent Claim
35 words
The semiconductor memory device as set forth in claim 6, in which said first logic circuits include address decoders, selectors and controllers for an addressing system, and said second logic circuits include sense amplifiers (52a).
Claim 8
Dependent Claim
28 words
The semiconductor memory device as set forth in claim 6, in which a memory cell incorporated in said memory cell array (51) includes a switching field-effect transistor (SW).
Claim 9
Dependent Claim
49 words
The semiconductor memory device as set forth in claim 8, in which said second logic circuits (52a) includes at least one field effect transistor (Qn2) having source and drain regions (52b/52c) thicker than source and drain regions (31b/31c) of said switching field-effect transistor (SW) included in said memory cell.
References Cited (Backward Citations)
No citation records indexed.
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