Semiconductor device

Claim 2

The semiconductor device according to claim 1, wherein said substrate bias generating means includes: first bias voltage generating means for generating a first bias potential of a magnitude selected to minimize leak current of the transistor at the standby state, and second bias potential generating means for generating a second bias potential of a magnitude selected to maximize drivability of the transistor at the active state.

Claim 3

The semiconductor device according to claim 2, wherein said substrate bias potential generating means includes selecting means responsive to a control signal for designating operation of the transistor for selecting either said first bias potential generating means or said second bias potential generating means.

Claim 4

The semiconductor device according to claim 2, wherein said bias potential generating means includes first setting means for setting said first bias potential at a value minimizing leak current of the transistor at the standby state.

Claim 5

The semiconductor device according to claim 2, wherein said transistor operates receiving first and second operating potentials; and said second bias potential generating means includes second setting means for setting said second operating potential at a value maximizing drivability of the transistor at the active state.

Claim 6

The semiconductor device according to claim 4, wherein said first setting means includes oscillating means for generating a signal of a predetermined frequency, and converting means for converting the signal generated by said oscillating means to said first bias potential.

Claim 7

The semiconductor device according to claim 3, wherein said selecting means includes first switching means connected between a substrate terminal of the transistor and said first bias potential generating means and turning on in response to a control signal for setting said transistor to the standby state; and second switching means connected between the substrate terminal of the transistor and said second bias potential generating means and turning on in response to a control signal for setting said transistor to the active state.

Claim 8

A semiconductor device comprising: a semiconductor substrate; an MOS transistor on said substrate, receiving first and second operating potentials and operative selectively in active and standby states; and substrate bias potential generating means responsive to a control signal designating operation of the transistor (i) in the potential (Vbb) and (ii) in the active state for applying to said substrate the second operating potential.

Claim 9

The semiconductor device according to claim 8, wherein said substrate bias potential generating means includes first bias potential generating means for generating said back bias potential at the standby state.

Claim 10

The semiconductor device according to claim 9, wherein said substrate bias potential generating means includes selecting means responsive to a control signal for designating operation of the transistor for selecting either said back bias potential generated by said first bias potential generating means or said second operating potential.

Claim 11

The semiconductor device according to claim 9, wherein said first bias potential generating means includes setting means for setting said back bias potential at a potential of a magnitude selected to minimise leak current of the transistor.

Claim 12

A semiconductor device comprising: a semiconductor substrate; an MOS transistor on said substrate, receiving first and second operating potentials and operative selectively in active and standby states; and substrate bias potential generating means responsive to a control signal designating operation of the transistor (i) in the standby state for applying to said substrate a bias potential (Vbb) of a magnitude selected to minimise leak current of the transistor, and (ii) in the active state for applying to said substrate the second operating potential.

Claim 13

The semiconductor device according to claim 12, wherein said substrate bias potential generating means includes first bias potential generating means for generating a first bias potential of a magnitude selected to minimise leak current of the transistor at the standby state.

Claim 14

The semiconductor device according to claim 13, wherein said substrate bias potential generating means includes selecting means responsive to a control signal for designating operation of the transistor for selecting either said first bias potential or said second operating potential.

Claim 15

The semiconductor device according to claim 13, wherein said bias potential generating means includes setting means for setting the first bias potential at a value minimizing leak current of the transistor at the standby state.

Claim 16

A semiconductor device comprising: a semiconductor substrate; an MOS transistor on said substrate, receiving first and second operating potentials and operative selectively in active and standby states; and substrate bias potential generating means responsive to a control signal designating operation of the transistor (i) in the standby state for applying to said substrate a bias potential (Vbb) of a magnitude selected to minimise power consumption defined by (a) power consumption of the substrate bias potential generating means when the transistor is activated and in the standby state, and (b) power comnsumption as a result of leakage current of the transistor, and (ii) in the active state for applying to said substrate the second operating potential.

Claim 17

The semiconductor device according to claim 16, wherein said substrate bias potential generating means includes first bias potential generating means for generating said bias potential for minimising power consumption at the standby state.

Claim 18

The semiconductor device according to claim 17, wherein said substrate bias generating means includes selecting means responsive to a control signal for designating operation of the transistor for selecting either said first bias potential or said second operating potential.

Claim 19

The semiconductor device according to claim 17, wherein said first bias potential generating means includes setting means for setting said first bias potential to a value minimising leak current of the transistor at the standby state.

Claim 20

The semiconductor device according to any one of claims 1, 8, 12 or 16, wherein said MOS transistor includes a first MOS transistor of a certain conductivity type and a second MOS transistor of a conductivity type opposite to said certain conductivity type; and said first MOS transistor and said second MOS transistor receive the first and second operating potentials and turn on/off complementarily.

Claim 21

The semiconductor device according to claim 20, wherein said first operating potential is the supply voltage and said second operating potential is the ground potential.

Claim 22

The semiconductor device according to claim 20, wherein said first MOS transistor includes a first substrate terminal receiving a bias potential of a magnitude to minimise leak current at the standby state and receiving said second operating potential at the active state.

Claim 23

The semiconductor device according to claim 20, wherein said MOS transistor includes a second substrate terminal receiving a bias potential of a magnitude selected to minimise leak current at the standby state and receiving said first operating potential at the active state.

Claim 24

The semiconductor device according to any one of claims 1, 8, 12 or 16 wherein said MOS transistor includes a transistor having a semiconductor layer on an insulating layer.

Claim 25

The semiconductor device according to claim 24, wherein said transistor having a semiconductor layer formed on the insulating layer includes a backgate provided at a position corresponding to a gate electrode in said insulating layer for receiving a bias potential of a magnitude selected to minimize leak current of the transistor at the standby state and receiving a bias potential of a magnitude selected to maximize drivability of the transistor at the active state.

Claim 26

A semiconductor device including a semiconductor substrate (1) and an internal circuit (110) including a MOS transistor formed on said semiconductor substrate (1), comprising: means (30) for generating a first bias voltage (VBB1) for minimizing a magnitude of leak current in an inactive state of said MOS transistor; means (31) for generating a second bias voltage (VBB2) for maximizing drivability of supplying current in an active state of said MOS transistor with the bias made shallower than said first bias voltage (VBB1); and means (32) responsive to a signal (CNT) for rendering active said MOS transistor for supplying said second bias voltage (VBB2) instead of said first bias voltage (VBB1) to said semiconductor substrate (1).

Claim 27

The semiconductor device according to claim 26, wherein said amount of leak current is determined based on a relation between drain current and threshold voltage of said MOS transistor in an inactive state, said first bias voltage (VBB1) is determined to be a potential which makes the threshold voltage of said MOS transistor be the threshold voltage in said inactive state, and said second bias voltage (VBB2) is determined based on a relation between the drain current and the threshold voltage of said MOS transistor in the active state.

Claim 28

The semiconductor device according to claim 26, wherein said means (30, 31) for generating first and second bias voltages each include oscillating means (301, 311) for generating a signal of a predetermined frequency, and converting means (302, 312) for converting the signal generated by said ring oscillator (30, 31) to a predetermined negative DC voltage.

Claim 29

The semiconductor device according to claim 26, wherein said MOS transistor includes a substrate terminal, and said bias supplying means (32) includes first switching means (321) connected between said substrate terminal and said means (30) for generating a first bias voltage (VBB1) and turning on in response to a signal for rendering inactive said MOS transistor, and second switching means (322) connected between said substrate terminal and said means (31) for generating a second bias voltage (VBB2) and turning on in response to a signal for rendering active said MOS transistor.

Claim 30

A semiconductor device including a semiconductor substrate (1) and a CMOS circuit including a MOS transistor (11) of a first conductivity type and a MOS transistor (12) of a second conductivity type formed on said semiconductor substrate (1), comprising: means (30) for generating a first bias voltage (VBB1) for minimizing a magnitude of leak current of said MOS transistor (11) of the first conductivity type in an inactive state; means (33) for generating a third bias voltage (VBB3) for minimizing a magnitude of leak current of said MOS transistor of the second conductivity in an inactive state; means (31) for generating a second bias voltage (VBB2) for maximizing drivability of supplying current of said MOS transistor (11) of the first conductivity type in an active state with the bias made shallower than said first bias voltage (VBB1); means for generating a fourth bias voltage (VBB4) for maximizing drivability of supplying current of said MOS transistor (12) of the second conductivity type in the active state, with the bias made shallower than said third bias voltage (VBB3); and means (32) responsive to a signal for activating said CMOS circuit for supplying said second bias voltage (VBB2) to a well region (6) of said MOS transistor (11) of the first conductivity type instead of said first bias voltage (VBB1), and for supplying said fourth bias voltage (VBB4) to a well region (10) of said MOS transistor (12) of the second conductivity type instead of said third bias voltage (VBB3).

Claim 31

The semiconductor device according to claim 30, wherein said MOS transistor (11) of the first conductivity type is an N channel MOS transistor, and said MOS transistor (12) of the second conductivity type is a P channel MOS transistor; said first bias voltage (VBB1) is determined based on a relation between drain current and threshold voltage of said N channel MOS transistor (11) in the inactive state; said second bias voltage (VBB2) is determined based on a relation between the drain current and the threshold voltage of said N channel MOS transistor (11) in the active state; said third bias voltage (VBB3) is determined based on a relation between drain current and threshold voltage of said P channel MOS transistor (12) in the inactive state; and said fourth bias voltage (VDD4) is determined based on a relation between the drain current and the threshold voltage of said P channel transistor (12) in the active state.

Claim 32

The semiconductor device according to claim 30, wherein said bias supplying means includes first switching means (32) connected between the well region (6) of said MOS transistor (11) of the first conductivity type and said means (30) for generating the first bias voltage (VBB1) and turning on in response to a signal (/CNT) for inactivating said CMOS circuit, second switching means (322) connected between the well region (6) of said MOS transistor (11) of the first conductivity type and said means (31) for generating the second bias voltage (VBB2) and turning on in response to a signal for activating (CNT) said CMOS circuit, third switching means (323) connected between the well region (10) of said MOS transistor (12) of the second conductivity type and said means (33) for generating the third bias voltage (VBB3) and turning on in response to a signal (/CNT) for inactivating said CMOS circuit, and fourth switching means (324) connected between the well region (10) of said MOS transistor (12) of the second conductivity type and said means (34) for generating fourth bias voltage (VBB4) and turning on in response to a signal (CNT) for activating said CMOS circuit.

Claim 33

A semiconductor device including a semiconductor substrate (1), a buried insulator layer (14) formed on said semiconductor substrate (1), a semiconductor layer (13) formed on said buried insulator layer (14) and an internal circuit including a MOS transistor (11, 12) formed on said semiconductor layer (13), comprising: means (30) for generating a first bias voltage (VBB1) for minimizing a magnitude of leak current of said MOS transistor (11, 12) in an inactive state; means (30) for generating a second bias voltage (VBB1) for maximizing current supplying drivability of said MOS transistor (11, 12) in an active state with the bias made shallower than said first bias voltage (VBB1); and means (32) responsive to a signal (CNT) for activating said MOS transistor (11, 12) for supplying said second bias voltage (VBB2) to said semiconductor substrate (1) instead of said first bias voltage (VBB1).

Claim 34

A semiconductor device including a semiconductor substrate (1), a buried insulator layer (14) formed on said semiconductor substrate (1), a semiconductor layer (13) formed on said buried insulator layer (14), and a CMOS circuit including a MOS transistor (11) of a first conductivity type and a MOS transistor (12) of a second conductivity type formed on said semiconductor layer (13), comprising: first region (18) provided in said buried insulator layer (14) below said MOS transistor (11) of the first conductivity type; a second region (19) provided in said buried insulator layer (14) below said MOS transistor (12) of the second conductivity type; means (30) for generating a first bias voltage (VBB1) for determining an amount of leak current of said MOS transistor (11) of the first conductivity type in an inactive state; means (33) for generating a third bias voltage (VBB3) for determining an amount of leak current of said MOS transistor (12) of the second conductivity type in an inactive state; means (31) for generating a second bias voltage (VBB2) for determining drivability of supplying current of said MOS transistor (11) of the first conductivity type in the active state with the bias made shallower than said first bias voltage; means (34) for generating a fourth bias voltage (VBB4) for determining drivability of driving current of said MOS transistor (12) of the second conductivity type in the active state with the bias made shallower than said third bias voltage (VBB4); and means (32) responsive to a signal (CNT) for activating said CMOS circuit for supplying said second bias voltage (VBB2) to said first region (16) instead of said first bias voltage (VBB1) and for supplying said fourth bias voltage (VBB4) to said second region instead (19) of said third bias voltage (VBB3).