A capacitorless dram device on silicon-on-insulator substrate

Claim 2

The memory cell as defined by Claim 1, wherein said first conductivity type is n- type and said second conductivity type is p- type.

Claim 3

The memory cell as defined by Claim 2, wherein electrons from said buried word line region (16) flow into said storage node (24) in writing into said cell and increasing conductance of said read transistor.

Claim 4

The memory cell as defined by Claim 2, wherein said storage node (24) is charged with a positive voltage from said write bit line region (12) in writing into said cell and increasing threshold voltage of said read transistor.

Claim 5

The memory cell as defined by Claim 4, wherein said body comprises a silicon substrate (22) with said first insulating layer (20) comprising silicon oxide and said semiconductor layer comprising silicon.

Claim 6

The memory cell as defined by Claim 1, wherein said body comprises a silicon substrate (22) with said first insulating layer (20) comprising silicon oxide and said semiconductor layer comprising silicon.

Claim 7

A dynamic random access memory comprising an array of memory cells arranged in rows and columns, and characterised in that each memory cell comprises a body including a supporting substrate, a first dielectric insulating layer (20) on said substrate, and a semiconductor layer (18) on said first dielectric insulating layer (20), said semiconductor layer (18) having a surface, a storage node (24) in said semiconductor layer abutting said surface, and electrically isolated from said substrate by said first dielectric insulating layer (20), said storage node having a net dopant concentration of a first conductivity type, a write bit line region (12) abutting said surface and spaced from said storage node (24), said write bit line region (12) having a net dopant concentration of said first conductivity type, a buried word line region (16) abutting said surface and positioned between and abutting said storage node (24) and said write bit line region (12), said buried word line region (16) having a net dopant concentration of a second conductivity type, a read bit line region (14) abutting said surface and said storage node (24) opposite from said buried word line region (16), said read bit line region (14) having a net dopant concentration of said second conductivity type, a second dielectric insulating layer (11) on said surface, and a gate electrode (10) on said second dielectric insulating layer (11) positioned over said storage node (24) and said buried word line region (16), said gate electrode (10) functioning with said write bit line region (12), said buried word line region (16), and said storage node (24) as a write transistor, and said gate electrode (10) functioning with said buried word line region (16), said storage node (24), and said read bit line region (14) as a read transistor, wherein said body of each memory cell comprises a portion of a common substrate.

Claim 8

The dynamic random access memory as defined by Claim 7 and including a conductive word line interconnecting all gate electrodes of cells along a row, and at least one conductive bit line interconnected to cells along a column.

Claim 9

The dynamic random access memory as defined by Claim 8 and including switch means for selectively connecting said at least one conductive bit line to all write bit line regions in said column and to all read bit line regions in said column.

Claim 10

The dynamic random access memory as defined by Claim 8 and including a write bit line connected to all write bit line regions in said column and a read bit line connected to all read bit line regions in said column.