Storage device

Claim 2

A cell according to claim 1 wherein the capacitance per unit area between said control gate (1;51;75;91) and said floating gate (2;56;96) is higher than that between said floating gate (2;56;96) and said channel (3;58;76;98), the area of said floating gate (2;56;96) thus being larger than the overlapping area of said control gate (1;51;75;91) and said floating gate(2;56;96).

Claim 3

A cell according to claim 2 wherein said floating gate is interposed between said control gate and said channel leaving no area of direct overlap between said control gate and said channel.

Claim 4

A cell according to any of claims 1 to 3 wherein said source and drain are defined in a well (58;133) region of a semiconductor substrate (60;-), said channel being a part of said well, extending between said source and said drain.

Claim 5

A cell according to any of claims 1 to 3 wherein said source (54) and drain (54) are defined in an isolated portion (80) of a semiconductive active layer (77,78) on an insulative substrate (71), said channel being a part of said isolated portion (80) of said semiconductive active layer, extending between said source and said drain.

Claim 6

A cell according to either of claims 4 or 5 wherein said floating gate insulator layer (104;113) and said floating gate (96;112) extend vertically down each side of said channel (98;108) to increase the capacitance therebetween.

Claim 7

A cell according to any preceding claim wherein said floating gate insulator layer is of silicon oxynitride (SiON) and said floating gate is of doped polycrystalline silicon (poly-Si).

Claim 8

A cell according to any preceding claim, being once programmed and having thus said antifuse in said low-resistance state.

Claim 9

An OT-PROM memory array comprising: a plurality of memory cells (11-44) arranged in rows and columns, each cell being a cell as claimed in any one of the preceding claims 1 to 7; a plurality of word lines extending in parallel in the row direction, respective word lines connecting the control gates of the cells arranged in respective rows; and a plurality of bit lines extending in parallel in the column direction, respective bit lines connecting the channels of the cells arranged in respective columns.

Claim 10

An array according to claim 9 wherein in each column the cells (11-41; 12-42, 13-43, 14-44) are connected in series.

Claim 11

An array according to claim 10 wherein the adjacent cells in each column have a common source/drain electrode (54) therebetween.

Claim 12

An array according to claim 9 wherein in each column the cells (11-41; 12-42, 13-43, 14-44) are connected in parallel, in each column the sources of the cells being connected to a source line (122,123) and the drains of the cells being connected to a drain line (120,121).

Claim 13

An array according to claim 12 wherein in each column the sources are co-extensive and define the source line and the drains are co-extensive and define the drain line.

Claim 14

An array according to any of claims 9 to 13 comprising as said plurality of memory cells, cells as claimed in either of claims 4 or 5, wherein in each column said wells (58;98) or said isolated regions (76;108) are co-extensive.

Claim 15

An array according to claim 14 wherein said co-extensive wells (58;98) or isolated regions (108) are shunted with a higher concentration impurity semiconductor (63;82; 107) of the same conductivity type.

Claim 16

An array according to any of claims 9 to 15 once programmed and having thus the antifuses of selected cells in said low-resistance state, and the antifuses of non-selected cells in said high-resistance state.

Claim 18

A memory programming circuit for performing the method of claim 17, said circuit comprising: the array of any of claims 9 to 15; a row decoder (10) and a row driver (9), cooperative therewith, for applying the pulse voltage V 1 to the wordline of the row including the selected cell, and for grounding the wordlines of the rows not including the selected cell; a ground line (-,SW12); an array of switches (SW5-SW8) interposed between the bit lines of said array and said ground line; a column decoder (8) arranged to control said array of switches to ground the bit line of the column including the selected cell whilst isolating the bit lines of the columns not including the selected cell; grounding means (7, SW1-SW4, SW10,SW11) for grounding the sources and drains of all said cells; and address means (18 to 20) to supply the row and column addresses of the selected cell to said row decoder and said column decoder.

Claim 19

A method of reading the array of claim 16 performed by: setting the bit-line of a selected column at supply voltage V CC ; precharging the source and drain of each cell of the selected column to the supply voltage; applying a reading pulse of voltage V 2 to the wordline of a selected row, wherein V 2 satisfies the following inequalities: V 2 > Vth; V 2 < Vth (1 + C FG /C CG ) where Vth is the threshold value of the transistor having the source, drain, channel and floating gate of the selected cell, grounding the end source or source line of the selected row; and sensing the voltage on the end drain or drainline to read the voltage of the cell included in the selected row and selected column.

Claim 20

A memory reading circuit for performing the method of claim 19, said circuit comprising: the array of claim 16; a row decoder (10) and a row driver (9), cooperative therewith, for grounding the wordlines during precharging, for applying the reading pulse V 2 to the wordline of the selected row, and for grounding the wordlines of the non-selected rows during reading; a sense line; a first switch array (SW1-SW4) interposed between said sense line and the end drains or drain lines of said array; a first column decoder (7) for controlling said first switch array to connect the end drains or draw line of a selected column to said sense line for precharging and for sensing; a common line connected to the end sources or sense lines; a channel bias line; a second switch array (SW5-SW8) interposed between the bit lines of said array and said channel bias line; a second column decoder (8) for controlling said second switch array to connect the bit line of the selected column to said channel bias line whilst isolating the bit lines of non-selected columns from said bit line; switching means (SW9-SW13) for switching the sense line to the supply voltage V CC for precharging, for isolating the sense line from supply voltage and from ground for sensing, and for grounding the sense line after sensing, for isolating the common line during precharging, and for grounding the common line during reading, for switching the channel bias line to supply voltage V CC for precharging and reading, and for grounding the channel bias line during resetting; control means (25) for controlling the operation of said switching means in accordance with the method of claim 19; and address means (17-20) to supply the row & column addresses of a selected cell to said row decoder and said first and second column decoders.

Claim 21

A memory circuit for performing the method of each of claims 17 and 19, said circuit comprising: an array according to any of claims 9 to 15; a row decoder (10), and a row driver (9) cooperative therewith, for applying said voltages to the wordlines of selected rows and for grounding non-selected rows of said array; a sense line; a first array of switches (SW1-SW4) interposed between said sense line and the end drain or drain lines of the columns of said array; a first column decoder (7) for controlling said first array of switches; a common line connected to the end sources or source lines of said array; a channel bias line; a second array of switches (SW5-SW8) interposed between said channel bias line and the bit lines of the array; a second column decoder for controlling the second array of switches; address means to supply the row and column addresses of a selected cell to said row decoder and said first and second column decoders; switching means for isolating said sense line, common line and channel bias line from supply voltage V CC and ground, and for switching them to supply voltage V CC or ground; and control means for co-ordinating operation of said address means and switching means in accordance with the method of claims 17 and 19.

Claim 22

A memory circuit as claimed in claim 21 having said memory array (hereinafter said first memory array); a second memory array of SRAM, DRAM or flash memory type ;and means for writing and reading data therein; data input means for supplying same data to be written both in said first memory array and in said second memory array; and a comparator for comparing the results of reading said first and second memory arrays.

Claim 23

A memory circuit according to claim 22 arranged for storing the results of comparison by said comparator in said first memory array.

Claim 24

A memory circuit according to either of claims 22 or 23, wherein said memory circuit is a NOR logic gate comprised of transistors which are replicas of the cells of said first memory array.

Claim 25

A memory circuit according to any preceding claim 18 to 24 mounted on a card.

Claim 26

A memory circuit according to claim 25 having a light receiving element and a light-emitting element arranged for inputting and outputting information.