Semiconductor device

Claim 2

The device as claimed in claim 1, wherein said hemispherical like shape silicon grain has a diameter in a range of 30 to 170 nm.

Claim 3

A semiconductor device comprising a polycrystalline silicon layer, a dielectric layer formed on said polycrystalline silicon layer, and a conductive layer formed on said dielectric layer, said polycrystalline silicon layer having a top surface and a side surface, said top surface being made uneven with a plurality of convex portions, each of said convex portions being defined by a silicon grain of a mushroom like shape.

Claim 4

The device as claimed in claim 3, wherein said mushroom like shape silicon grain has a diameter in range of 30 to 170 nm.

Claim 5

The device as claimed in claim 3, wherein said side surface of said polycrystalline silicon layer is made uneven with a plurality of convex portions, each of said convex portions being defined by a silicon grain of a mushroom like shape.

Claim 6

A semiconductor device comprising a polycrystalline silicon layer, a dielectric layer formed on said polycrystalline silicon layer, and a conductive layer formed on said dielectric layer, said polycrystalline silicon layer having an uneven surface including a plurality of convex portions, each of said convex portions being defined by a silicon grain of a mushroom like shape, said silicon grain has a first diameter defining a stem of said mushroom like shape and a second diameter defining a bulging portion of said mushroom like shape, said first diameter being smaller than said second diameter.

Claim 7

The device as claimed in claim 1, wherein said polycrystalline silicon layer, said dielectric layer and said conductive layer are employed as a lower electrode, a dielectric and an upper electrode of a capacitor in a dynamic memory cell, respectively.

Claim 8

The device as claimed in claim 3, wherein said polycrystalline silicon layer, said dielectric layer and said conductive layer are employed as a lower electrode, a dielectric and an upper electrode of a capacitor in a dynamic memory cell, respectively.

Claim 9

The device as claimed in claim 5, wherein said polycrystalline silicon layer, said dielectric layer and said conductive layer are employed as a lower electrode, a dielectric and an upper electrode of a capacitor in a dynamic memory cell, respectively.

Claim 10

A semiconductor capacitor formed on a substrate comprising: a first electrode having a plurality of mushroom like shaped convex silicon grains creating an uneven surface; a dielectric layer formed on said first electrode with a thickness such that a pair of opposing surfaces of said dielectric layer are substantially parallel and substantially replicate said uneven surface of said first electrode; a second electrode formed on and conformal to said dielectric layer is insulated from said first electrode, whereby capacitance between said first electrode and said second electrode is increased by said mushroom like shape silicon grains of said uneven surface.

Claim 11

The device as claimed in claim 10, wherein said silicon grain has a first diameter defining a stem of said mushroom like shape and a second diameter defining a bulging portion of said mushroom like shape, said first diameter being smaller than said second diameter.

Claim 12

The device as claimed in claim 11, wherein said dielectric thickness is in the range of 30 angstroms to 500 angstroms.

Claim 13

The device as claimed in claim 12, wherein said dielectric is comprised of Si 3 N 4 and SiO 2 .

Claim 14

The device as claimed in claim 13, wherein said second electrode is made of polycrystalline silicon.

Claim 15

The device as claimed in claim 10, wherein said increased capacitance is at least two times the capacitance of a capacitor with a first electrode having an ordinary polycrystalline silicon surface.