US6424016B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
SOI DRAM having P-doped polysilicon gate for a memory pass transistor
Assignee: Autoliv Development AB
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Filing: 1997-05-23
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Granted: 2002-07-23
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Expires: 2017-05-23
Abstract
Abstract An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substantially near mid-gap work function or greater. The DRAM also includes a peripheral area including a plurality of logic transistors. In a preferred embodiment the pass gate transistors are silicon-on-insulator transistors.
Inventors
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:26
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10B12/50; H10D; H10D86/00; H10D86/01; H10D86/201; H10B12/02; H10B12/05; H10D89/00; H10D89/211; H10D89/213
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
55 words
An integrated circuit including a DRAM, said DRAM comprising: a memory array including a plurality of pass gate transistors and a plurality of memory elements; said pass gate transistors each having a gate material selected to provide a substantially near mid-gap work function or greater; and a peripheral area including a plurality of logic transistors.
Claim 2
Dependent Claim
55 words
An integrated circuit including a DRAM, said DRAM comprising: a memory array including a plurality of pass gate transistors and a plurality of memory elements; said pass gate transistors each having a gate material selected to provide a substantially near mid-gap work function or greater; and a peripheral area including a plurality of logic transistors.
Claim 3
Dependent Claim
14 words
The integrated circuit of claim 1 wherein said pass gate transistors are silicon-on-insulator transistors.
Claim 4
Dependent Claim
30 words
The integrated circuit of claim 1 wherein the gate material of said logic transistors are of the same type of material as said gate material for said pass gate transistors.
Claim 5
Dependent Claim
20 words
The integrated circuit of claim 1 wherein said pass gate transistors are n-channel devices with p doped polysilicon gate regions.
Claim 6
Dependent Claim
19 words
The integrated circuit of claim 1 wherein said pass gate transistors are p-channel devices with n-doped polysilicon gate regions.
Claim 7
Dependent Claim
19 words
The integrated circuit of claim 1 wherein said pass gate transistors are n-channel devices with titanium nitride gate regions.
Claim 8
Dependent Claim
19 words
The integrated circuit of claim 1 wherein said pass gate transistors are p-channel devices with titanium nitride gate regions.
Claim 9
Dependent Claim
13 words
The integrated circuit of claim 2 wherein said logic transistors are silicon-on-insulator transistors.
Claim 10
Dependent Claim
16 words
The integrated circuit of claim 2 wherein said pass gate transistors are fully depleted silicon-on-insulator transistors.
Claim 11
Dependent Claim
25 words
The integrated circuit of claim 8 wherein said pass gate transistors are fully depleted silicon-on-insulator transistors and said logic transistors comprise partially depleted silicon-on-insulator transistors.
Claim 12
Dependent Claim
31 words
The integrated circuit of claim 2 wherein the silicon film thickness for said pass gate transistors is thinner than the silicon film thickness for at least one of said logic transistors.
Claim 13
Dependent Claim
28 words
The integrated circuit of claim 10 wherein the silicon film thickness for said pass gate transistors is the same as the silicon film thickness for the logic transistors.
Claim 14
Dependent Claim
15 words
The integrated circuit of claim 1 wherein said pass gate transistors are inversion mode transistors.
Claim 15
Dependent Claim
15 words
The integrated circuit of claim 1 wherein said pass gate transistors are accumulation mode transistors.
Claim 16
Dependent Claim
24 words
The integrated circuit of claim 1 wherein said pass gate transistors are n-channel transistors and said logic transistors comprise n-channel transistors and p-channel transistors.
Claim 17
Dependent Claim
65 words
An integrated circuit including a DRAM device, said DRAM device comprising: a memory array including a plurality of pass gate transistors and a plurality of memory elements; said pass gate transistors each comprising n-channel devices having P+ doped polysilicon gate regions and fully depleted channel regions; and a peripheral area including a plurality of logic transistors, said logic transistors each having partially depleted channel regions.
Claim 18
Dependent Claim
65 words
An integrated circuit including a DRAM device, said DRAM device comprising: a memory array including a plurality of pass gate transistors and a plurality of memory elements; said pass gate transistors each comprising n-channel devices having P+ doped polysilicon gate regions and fully depleted channel regions; and a peripheral area including a plurality of logic transistors, said logic transistors each having partially depleted channel regions.
Claim 19
Dependent Claim
19 words
The integrated circuit of claim 16 wherein said P+ doped polysilicon gate regions are clad with a metal layer.
Claim 20
Dependent Claim
12 words
The integrated circuit of claim 17 wherein said metal layer comprises tungsten.
Claim 21
Dependent Claim
17 words
The integrated circuit of claim 16 further including a silicide layer on said P+ polysilicon gate regions.
Claim 22
Dependent Claim
49 words
An integrated circuit including a DRAM device, said DRAM comprising: a memory array including a plurality of pass gate transistors and a plurality of memory elements; said pass gate transistors comprising n-channel devices having P+ doped polysilicon gate regions; and a peripheral area including a plurality of logic transistors.
Claim 23
Dependent Claim
49 words
An integrated circuit including a DRAM device, said DRAM comprising: a memory array including a plurality of pass gate transistors and a plurality of memory elements; said pass gate transistors comprising n-channel devices having P+ doped polysilicon gate regions; and a peripheral area including a plurality of logic transistors.
Claim 24
Dependent Claim
19 words
The integrated circuit of claim 20 wherein said P+ doped polysilicon gate regions are clad with a metal layer.
Claim 25
Dependent Claim
12 words
The integrated circuit of claim 21 wherein said metal layer comprises tungsten.
Claim 26
Dependent Claim
17 words
The integrated circuit of claim 20 further including a silicide layer on said P+ polysilicon gate regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-07-22 | 2006-01-21 | 2006-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-22 | 2010-01-21 | 2010-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-22 | 2014-01-21 | 2014-07-23 | $7700.00 | Window Closed / Lapsed |