US4888631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor dynamic memory device
Assignee: Sharp Corp
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Filing: 1988-11-03
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Granted: 1989-12-19
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Expires: 2008-11-03
Abstract
Abstract A semiconductor IC element is three-dimensionally structured with a first active layer formed on a single crystalline silicon substrate and a second active layer formed by melting polycrystalline silicon by irradiation on an insulative layer which electrically insulates it from the first layer. Each active layer is comprised of single crystalline areas where transistors may be formed and separation areas which insulate them. PMOS, NMOS or CMOS field effective transistors are formed on these active element areas. A test circuit for testing the originally intended functions of the element as well as its redundant circuits may be formed on these layers. Throughholes are provided to connect the vertically separated active layers.
Inventors
- 👤 Daisuke Azuma
- 👤 Yoshiji Ohta
- 👤 Shinichi Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:44
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10D; H10D88/00; H10D99/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
206 words
A semiconductor dynamic memory device of three-dimensionally stacked structure comprising a first active layer which is flat and is formed on a single crystalline silicon substrate, a second active layer which is flat and is obtained by melting polycrystalline silicon by irradiation on an insulative layer which electrically insulates said first active layer from said second active layer, and throughholes connecting said active layers across said insulative layer, each of said active layers comprising single crystalline active element areas which serve to have transistors formed therein, separation areas which individually insulate said active element areas and passive element areas which serve to have plane capacitors, said active element areas and said separation areas having selected widths, PMOS, NMOS or CMOS field effect transistors being formed in said active element areas of each of said active layers, plane capacitors being formed in said passive element areas of each of said active layers, each of said transistors in said first active layer being connected to one of said plane capacitors in said second active layer through one of said throughholes and each of said transistors in said second active layer being connected to one of said plane capacitors in said first active layer through another of said throughholes.
Claim 2
Dependent Claim
206 words
A semiconductor dynamic memory device of three-dimensionally stacked structure comprising a first active layer which is flat and is formed on a single crystalline silicon substrate, a second active layer which is flat and is obtained by melting polycrystalline silicon by irradiation on an insulative layer which electrically insulates said first active layer from said second active layer, and throughholes connecting said active layers across said insulative layer, each of said active layers comprising single crystalline active element areas which serve to have transistors formed therein, separation areas which individually insulate said active element areas and passive element areas which serve to have plane capacitors, said active element areas and said separation areas having selected widths, PMOS, NMOS or CMOS field effect transistors being formed in said active element areas of each of said active layers, plane capacitors being formed in said passive element areas of each of said active layers, each of said transistors in said first active layer being connected to one of said plane capacitors in said second active layer through one of said throughholes and each of said transistors in said second active layer being connected to one of said plane capacitors in said first active layer through another of said throughholes.
Claim 3
Dependent Claim
31 words
The semiconductor dynamic memory device of claim 1 wherein said first active layer is of SOI structure obtained by melting polycrystalline silicon by irradiation on another insulative layer on said substrate.
Claim 4
Dependent Claim
25 words
The semiconductor dynamic memory device of claim 1 further comprising a redundant circuit section contained in said first active layer and/or said second active layer.
Claim 5
Dependent Claim
49 words
The semiconductor dynamic memory device of claim 1 further comprising a test circuit for testing the functions originally intended for said active elements, and redundant circuits for said test circuit, said test circuit and said redundant circuits being contained in said first active layer or said second active layer.
Claim 6
Dependent Claim
31 words
The semiconductor dynamic memory device of claim 1 wherein said active layers are stacked one on top of another and said element comprises throughholes which connect said layers in perpendicular direction.
References Cited (Backward Citations)
US4489478A
Cited
US4485459A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-18 | 1993-06-19 | 1993-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-18 | 1997-06-19 | 1997-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-18 | 2001-06-19 | 2001-12-19 | $7700.00 | Window Closed / Lapsed |