Near-intrinsic thin-film SOI FETS

Claim 2

A field effect transistor device which comprises: a) an insulating layer; b) a substantially single crystal semiconducting film upon said insulating layer, said semiconducting film having a thickness of less than about 0.5 um in regions defining device channels, the film in said channel regions having a doping concentration of less than about 10 16 cm -3 , said film further defining source and drain regions having an impurity concentration higher than that of the channel regions; c) a gate dielectric upon the channel regions; and, d) a gate material upon the gate dielectric, said gate material having a work function such that the gate material has a Fermi level that is positioned at about the middle of the bandgap of the semiconducting film of the channel regions.

Claim 3

A field effect transistor as in claim 1 additionally comprising a substrate below the insulating layer.

Claim 4

A field effect transistor device as in claim 2 wherein the substrate comprises a semiconductor material.

Claim 5

A field effect transistor device as in claim 3 wherein the substrate comprises silicon.

Claim 6

A field effect transistor device as in claim 3 wherein the substrate comprises gallium arsenide.

Claim 7

A field effect transistor device as in claim 2 wherein the substrate comprises an insulating material.

Claim 8

A field effect transistor device as in claim 2 wherein the substrate comprises a conducting material.

Claim 9

A field effect transistor device as in claim 1 wherein the insulating layer comprises a material selected from the group consisting of insulating oxides, insulating nitrides and mixtures thereof.

Claim 10

A field effect transistor device as in claim 8 wherein the insulating layer comprises SiO 2 .

Claim 11

A field effect transistor device as in claim 1 wherein the semiconducting film comprises silicon.

Claim 12

A field effect transistor device as in claim 1 wherein the semiconducting film comprises gallium arsenide.

Claim 13

A field effect transistor device as in claim 1 wherein the semiconducting film has a thickness of approximately 0.25 um.

Claim 14

A field effect transistor device as in claim 1 wherein the doping concentration in the channel regions is below about 10 15 cm -3 .

Claim 15

A field effect transistor device as in claim 1 wherein the gate dielectric comprises a material selected from the group consisting of insulating oxides, insulating nitrides and mixtures thereof.

Claim 16

A field effect transistor device as in claim 14 wherein the gate dielectric comprises SiO 2 .

Claim 17

A field effect transistor device as in claim 10 wherein the gate material has a work function of between about 4.4 and about 5.0 eV.

Claim 18

A field effect transistor device as in claim 16 wherein the gate material is selected from the group consisting of refractory metals and silicides thereof.

Claim 19

A field effect transistor device as in claim 10 wherein the gate material comprises tungsten.

Claim 20

A field effect transistor device as in claim 10 wherein the gate material comprises tungsten silicide.

Claim 21

A field effect transistor device as in claim 10 wherein the gate material comprises molybdenum.

Claim 22

A field effect transistor device as in claim 10 wherein the gate material comprises molybdenum silicide.

Claim 23

A field effect transistor device which comprises: a) a silicon substrate; b) an oxide layer upon the substrate; c) a substantially single crystal silicon film upon the oxide layer, said silicon film having a thickness of less than about 0.5 um in areas defining device channel regions, the film in said channel regions having a doping concentration of less than about 10 16 cm -3 , said film further defining source and drain regions having an impurity concentration higher than that of the channel regions; d) a gate oxide upon the channel regions; and e) a gate material upon the gate oxide and positioned over the channel regions, said gate material having a work function of between about 4.4 and about 5.0 eV such that the gate material has a Fermi level positioned at about the middle of the bandgap of the silicon channel region.

Claim 24

A field effect transistor device which comprises: a) a silicon substrate; b) an oxide layer upon the substrate; c) a substantially single crystal silicon film upon the oxide layer, said silicon film having a thickness of less than about 0.5 um in areas defining device channel regions, the film in said channel regions having a doping concentration of less than about 10 16 cm -3 , said film further defining source and drain regions having an impurity concentration higher than that of the channel regions; d) a gate oxide upon the channel regions; and e) a gate material upon the gate oxide and positioned over the channel regions, said gate material having a work function of between about 4.4 and about 5.0 eV such that the gate material has a Fermi level positioned at about the middle of the bandgap of the silicon channel region.

Claim 25

A field effect transistor device as in claim 22 wherein the silicon film has a thickness of less than about 0.25 um.

Claim 26

A field effect transistor device as in claim 22 wherein the doping concentration in the channel regions is below about 10 15 cm -3 .

Claim 27

A field effect transistor device as in claim 22 wherein the gate material comprises tungsten.

Claim 28

In a near intrinsic, thin-film, semiconductor-on-insulator, field effect transistor characterized by having a substrate, a buried insulating layer, a near-intrinsic semiconductor film layer having a doping concentration of less than about 10 16 cm 31 3, a gate material upon a gate dielectric extending over the layer, the layer being patterned to define source, drain and channel regions; the improvement which comprises, as the gate material, a material having a work function which approximates its Fermi level to the middle of the bandgap of the semiconductor film material wherein the film comprises a single crystal epitaxial layer.

Claim 29

In a near intrinsic, thin-film, semiconductor-on-insulator, field effect transistor characterized by having a substrate, a buried insulating layer, a near-intrinsic semiconductor film layer having a doping concentration of less than about 10 16 cm 31 3, a gate material upon a gate dielectric extending over the layer, the layer being patterned to define source, drain and channel regions; the improvement which comprises, as the gate material, a material having a work function which approximates its Fermi level to the middle of the bandgap of the semiconductor film material wherein the film comprises a single crystal epitaxial layer.

Claim 30

The improvement of claim 26 wherein the semiconductor film material comprises silicon.

Claim 31

The improvement of claim 27 wherein the gate material has a work function of between about 4.4 and about 5.0 eV.

Claim 32

The improvement of claim 28 wherein the gate material is selected from the group consisting of refractory metals and silicides thereof.

Claim 33

The improvement of claim 27 wherein the gate material comprises tungsten.

Claim 34

The improvement of claim 26 wherein the semiconductor film material comprises gallium arsenide.

Claim 35

A complementary insulated gate field effect transistor circuit having both n-type and p-type transistors in which each transistor comprises: a) an insulating layer; b) a single crystal semiconducting film upon said insulating layer, said semiconducting film having a thickness of less than about 0.5 um in regions defining device channels, the film in said channel regions having a doping concentration of less than about 10 16 cm 31 3, said film further defining source and drain regions having an impurity concentration higher than that of the channel regions; c) a gate dielectric upon the channel regions; and d) a gate material upon the gate dielectric, the same gate material extending over the channel regions in both n-type and p-type transistors of the circuit, said gate material having a work function which approximates its Fermi level to the middle of the bandgap of the channel semiconductor material.

Claim 36

A complementary insulated gate field effect transistor circuit having both n-type and p-type transistors in which each transistor comprises: a) an insulating layer; b) a single crystal semiconducting film upon said insulating layer, said semiconducting film having a thickness of less than about 0.5 um in regions defining device channels, the film in said channel regions having a doping concentration of less than about 10 16 cm 31 3, said film further defining source and drain regions having an impurity concentration higher than that of the channel regions; c) a gate dielectric upon the channel regions; and d) a gate material upon the gate dielectric, the same gate material extending over the channel regions in both n-type and p-type transistors of the circuit, said gate material having a work function which approximates its Fermi level to the middle of the bandgap of the channel semiconductor material.

Claim 37

The circuit of claim 32 wherein the semiconductor film comprises silicon.

Claim 38

The circuit of claim 33 wherein the gate material comprises tungsten.

Claim 39

The circuit of claim 32 wherein the transistor channel regions of the n-type and p-type transistors are each doped with the same type of dopant.

Claim 40

The circuit of claim 35 wherein each transistor has an n-type channel doping.

Claim 41

The complementary insulated gate field effect transistor circuit of claim 32 wherein the threshold voltage is substantially the same for either p-type or n-type channel regions for each transistor.

Claim 42

The field effect transistor device of claim 1 wherein at least a portion of the semiconducting film comprises an epitaxial region.

Claim 43

The field effect transistor device of claim 1 wherein the film comprises silicon and the gate material has a work function between 4.4 and 5.0 eV.

Claim 44

The field effect transistor device of claim 1 wherein the device comprises an n-channel transistor with a threshold voltage under 0.3 Volts with no back-gate bias.