EP0063915A2
Expired / Lapsed
EP
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A metal insulator semiconductor transistor
Assignee: Fujitsu Ltd
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Filing: 1982-04-21
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Granted: —
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Expires: 2002-04-21
Abstract
Abstract An MIS transistor, which is built on an insulating layer (11) has the insulating layer (11) arranged with a thin portion (12) under the channel region (16) of the MIS transistor and a thick portion (13) under the remainder of the device, and has a conducting layer (19) formed beneath the insulating layer (11). Typically the device is a short channel MIS transistor having a channel length of 2.0 mu m or less. Such a transistor has the advantage that equipotential lines run generally parallel to the gate electrode (17) and have a reduced drain voltage feedback and an increased trans-conductance and punch-through voltage.
Inventors
- 👤 Junji Sakurai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 09:50
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6704; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D30/6758; H10P; H10P34/00; H10P34/40; H10P34/42
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
100 words
A metal insulator semiconductor transistor comprising an insulating layer (11); a semiconductor layer which is formed on the insulating layer (11) and which comprises a source region (14), a drain region (15) and a channel region (16); a gate insulating layer (17) formed on the channel region (16); and a gate electrode (18) formed on the gate insulating layer; characterised in that the portion (12) of the insulating layer (11) lying beneath the channel region (16) is thinner than that (13) lying beneath the other regions and in that a conducting layer (19) is formed beneath the insulating layer (11).
Claim 2
Dependent Claim
100 words
A metal insulator semiconductor transistor comprising an insulating layer (11); a semiconductor layer which is formed on the insulating layer (11) and which comprises a source region (14), a drain region (15) and a channel region (16); a gate insulating layer (17) formed on the channel region (16); and a gate electrode (18) formed on the gate insulating layer; characterised in that the portion (12) of the insulating layer (11) lying beneath the channel region (16) is thinner than that (13) lying beneath the other regions and in that a conducting layer (19) is formed beneath the insulating layer (11).
Claim 3
Dependent Claim
51 words
A transistor according to claim 1, in which the thinner portion (12) of the insulating layer (11) has a thickness in a range from 30 to 100 nm and that the thicker portion (13) of the insulating layer (11) has a thickness in a range from 500 nm to 2.0 µm.
Claim 4
Dependent Claim
22 words
A transistor according to claim 1 or 2, in which the insulating layer (11) is made from silicon dioxide or silicon nitride.
Claim 5
Dependent Claim
29 words
A transistor according to any one of the preceding claims, in which the conducting layer (19) is made from a substrate of a highly doped semiconductor, metal, or graphite.
Claim 6
Dependent Claim
39 words
A transistor according to claim 1, 2 or 3, in which the conducting layer (19) comprises a substrate of silicon, ceramic, glass, or high-temperature resin and a film overlying the substrate and made from tungsten, molybdenum, tantalum or aluminium.
Claim 7
Dependent Claim
34 words
A transistor according to claim 1, in which the conducting layer (19) is made from a single crystal silicon substrate having a conductive portion under the thinner portion (12) of the insulating layer (11).
Claim 8
Dependent Claim
20 words
A transistor according to claim 6, in which the conductive portion is a highly doped region of the silicon substrate.
Claim 9
Dependent Claim
15 words
A transistor according to claim 6, in which the conductive portion is a metal film.
Claim 10
Dependent Claim
39 words
A transistor according to claim 6, 7 or 8, in which another metal insulator semiconductor transistor is formed in a portion of the silicon substrate and is located close to the source (14), drain (15), and channel regions (l6).
References Cited (Backward Citations)
No citation records indexed.
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