EP0744772B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
DRAM storage cell with vertical transistor and method for production thereof
Assignee: Infineon Technologies AG
•
Filing: 1996-05-10
•
Granted: 2002-08-14
•
Expires: 2016-05-10
Abstract
Abstract In a DRAM cell arrangement with memory cells, each consisting of a read-out transistor and a storage capacitor, the novelty is that (a) the read-out transistor is a vertical MOS transistor which is integrated in a semiconductor substrate (2) and has one source/drain region (3) adjoining a main substrate face (1), the other source/drain region (5) adjoining a buried bit line (5) and the gate electrode (13) connected to a buried word line crossing the bit line (5); and (b) the storage capacitor is formed of a source/drain region (3) (as memory node) adjacent the main face (1), an overlying capacitor dielectric (16) and a capacitor plate (17). Also claimed is a method of producing the DRAM cell arrangement.
Inventors
- 👤 Wolfgang Dr. Rösner
- 👤 Lothar Dr. Risch
- 👤 Franz Dr. Hofmann
- 👤 Wolfgang Dr. Krautschneider
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:34
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/053; H10B12/30; H10B12/34
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
385 words
DRAM cell arrangement having memory cells which
each comprise a read-out transistor and a storage
capacitor, which arrangement includes the
following: a semiconductor substrate (2) which, at least
in the area of the DRAM cell arrangement, is
doped with a first conductivity type, the
semiconductor substrate (2) comprising pillars
which are arranged in rows and columns, adjoin
a main surface (1) of the semiconductor
substrate (2) and are formed by first and
second trenches (4, 7); each column having a region (3) which is doped
with a second conductivity type, which is
opposite to the first conductivity type, and a
region (2) which is doped with the first
conductivity type, the region (3) which is
doped with the second conductivity type in each
case adjoining the main surface (1) and, in the
area of the main surface (1), the flanks of the
respective pillar, and the region (2) which is
doped with the first conductivity type being
arranged beneath the region (3) which is doped
with the second conductivity type, adjoining
the flanks of the pillar and being connected to
the area of the semiconductor substrate (2)
which is doped with the first conductivity
type, buried bit lines (5), which are arranged at the
bottoms of the first trenches (4) and run
substantially parallel to one another; the read-out transistors being designed as
vertical MOS transistors which are integrated
in the pillars and of which one source/drain
region is the region (3) which is doped with
the second conductivity type and the other
source/drain region (5) is in each case a
buried bit line (5), the gate electrode (13) of
which is in each case arranged on a pillar wall
above a gate oxide (12); buried word lines (14), which are arranged in
the second trenches (7), run substantially
parallel to one another, cross the bit lines
(5) in an insulated manner and are insulated
with respect to the pillars, the gate
electrodes (13) in each case being connected to
one of the word lines (14); the storage capacitors in each case being
composed of one of the regions (3) which adjoin
the main surface (1) and are doped with the
second conductivity type, as storage node, a
capacitor dielectric (16) arranged above this
region and a capacitor plate (17) arranged
above the capacitor dielectric.
Claim 2
Dependent Claim
30 words
DRAM cell arrangement according to Claim 1, in
which the capacitor dielectric (16) is formed from
a material with a relative dielectric constant ε r of between 100 and 1000.
Claim 3
Dependent Claim
27 words
DRAM cell arrangement according to one of Claims 1
or 2, in which the capacitor dielectric (16) is
formed as a layer which covers the entire surface.
Claim 4
Dependent Claim
50 words
DRAM cell arrangement according to one of Claims 1
to 3, in which insulation structures (6, 15) are
provided, which only partially fill the area
between adjacent pillars, so that in the area of
the main surface (1) the flanks of the pillars are
partially covered with capacitor dielectric (16).
Claim 5
Dependent Claim
81 words
DRAM cell arrangement according to one of Claims 1
to 4, in which the width of the bit lines (5) and
of the word lines (14) and the distance between
adjacent bit lines (5) and between adjacent word
lines (14) are in each case substantially
identical, and in which the gate oxide (12) of the
vertical MOS transistors in each case partially
covers two adjacent flanks of a pillar, so that it
insulates the respective word line (14) from the
pillar.
Claim 6
Dependent Claim
69 words
DRAM cell arrangement according to one of Claims 1
to 5, in which the semiconductor substrate (2), at
least in the area of the DRAM cell arrangement,
comprises monocrystalline silicon, in which the insulation structures comprise
SiO 2 , in which the bit lines (5) are formed as doped
regions in the semiconductor substrate (2), in which the gate electrodes (13) and the word
lines (14) comprise doped polysilicon.
Claim 7
Dependent Claim
390 words
Method for fabricating a DRAM cell arrangement
according to Claim 1, in which, in the semiconductor substrate (2),
which, at least in an area for the DRAM cell
arrangement, is doped with a first conductivity
type, a region (3) which is doped with a second
conductivity type, which is opposite to the
first conductivity type, and adjoins a main
surface (1) of the semiconductor substrate (2),
is produced within this area, in which the first trenches (4) which run
substantially parallel to one another, are
produced in the semiconductor substrate (2), in which the bit lines (5) are produced at the
bottom of the first trenches (4), in which the first trenches (4) are then filled
with a first insulation structure (6), in which the second trenches (7), which cross
the first trenches (4) and extend at least as
far as the surface of the bit line (5), are
then produced, so that the pillars are formed, in which the second trenches (7) are filled
with a second insulation structure (8), the
height of which is less than the depth of the
second trenches (7), in which an anisotropic etch is carried out,
which attack the first insulation structure (6)
and the second insulation structure (8)
selectively with respect to the pillars the
semiconductor material and during which holes
(11) are etched, which extend from the main
surface (1) to the level of the bit lines (5)
and in which in each case one flank of the
pillars, which adjoins one of the second
trenches (7), is partially uncovered, in which gate oxides (12) are produced on the
uncovered flanks of the pillars, in which the gate electrodes (13), which in
each case fill up the width of the holes (11),
are produced in the holes (11), in which word lines (14), which are in each
case electrically connected to gate electrodes
(13) arranged along the respective second
trench (7), are produced in the second trenches
(7), in which a third insulation structure (15) is
produced in the second trenches (7), in which the capacitor dielectric (16) is
produced in such a manner that it covers at
least the surface of the pillars in the area of
the main surface (1), in which the capacitor plate (17) is produced
in such a manner that it covers at least the
pillars.
Claim 8
Dependent Claim
79 words
Method according to Claim 7, in which the first insulation structures (6)
and the third insulation structures (15) are
formed in such a way that they end at the same
level as the pillars, in which, in an etching process which is
selective with respect to the pillars, the
first insulation structures (6) and the third
insulation structures (15) are etched back,
steps, which are covered by the capacitor
dielectric (16) being formed on the flanks of
the pillars.
Claim 9
Dependent Claim
120 words
Method according to one of Claims 7 or 8, in which the first trenches (4) and the second
trenches (7) are formed with substantially the
same width, the distance between adjacent
trenches (4, 7) being substantially equal to
the width of the trenches, in which the holes (11) are etched using a mask
(9) with substantially square mask openings
(10), the side length of the square mask
openings (10) being substantially equal to the
width of the trenches (4, 7), in which the centre points of the square mask
openings (10) are arranged offset with respect
to the centres of the first trenches (4) and of
the second trenches (7) by less than one width
of the trenches (4, 7).
Claim 10
Dependent Claim
85 words
Method according to one of Claims 7 to 9, in which a substrate which, at least in the
area of the DRAM cell arrangement, comprises
monocrystalline silicon, is used as
semiconductor substrate (2), in which the insulation structures (6, 8, 15)
are formed from SiO 2 , in which the bit lines and the region (3) which
has been doped with the second conductivity
type are formed by implantation, in which the word lines (14) and the gate
electrodes (13) are formed from doped
polysilicon.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.