EP0245515B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Hitachi Ltd
•
Filing: 1986-11-12
•
Granted: 1997-04-16
•
Expires: 2006-11-12
Abstract
Abstract To prevent the injection of minority carriers into a substrate when the potential undergoes changes due to noise or the like. In a semiconductor device having a substrate and sources and drains of insulated gate-type field-effect transistors or having collectors, bases and emitters of bipolar transistors in a plurality of isolation layers that are electrically isolated in the substrate, a voltage is applied to the substrate or to said plurality of isolation layers, said voltage falling outside a range in which the voltage applied to said sources and drains or to said collectors, bases and emitters can be varied.
Inventors
- 👤 Goro Kitsukawa
- 👤 Kiyoo Itoh
- 👤 Ryoichi Hori
- 👤 Takao Watanabe
- 👤 Katsuhiro Shimohigashi
- 👤 Noriyuki Homma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:31
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10B; H10B12/00; H10B12/30; H10D84/40; H10D84/401; H10D84/856; H10D89/213
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
201 words
A semiconductor device formed within a first region of a substrate (p-Sub) of a first conductivity type (p) comprising a first well layer (nW) of the second conductivity type (n) formed within said first region, a second well layer (pW1, pW2) of the first conductivity type (p) formed within said first well layer (nW), a first insulated-gate field effect transistor (nMOS3) of a first channel type having source and drain of said second conductivity type (n) formed in said first region at its surface and a second insulated-gate field effect transistor (nMOS1, nMOS2) of the first channel type having source and drain of said second conductivity type (n) formed in said second well layer (pW1, pW2) at its surface, first voltage means to apply a first voltage (VBB4) to said first well layer (nW), second voltage means to apply and a second voltage (VBB2, VBB3) to said second well layer (pW1, pW2) and third voltage means to apply a third voltage (VBB1) to said first region, wherein the first voltage (VBB4) isolates the second well layer (pW1, pW2) and the first region, and wherein the value of said second voltage (VBB2, VBB3) is different from that of said third voltage (VBB1).
Claim 2
Dependent Claim
43 words
The semiconductor device according to claim 1, wherein a third insulated-gate field effect transistor (pMOS1, pMOS2) of the second channel type having source and drain of said first conductivity type (p) is formed in said first well layer (nW1, nW2) at its surface.
Claim 3
Dependent Claim
83 words
The semiconductor device according to claim 1 or 2, wherein a third well layer (nW3) of the second conductivity type (n) is formed within said first region, a fourth insulated-gate field effect transistor (pMOS3) of the second channel type having source and drain of said first conductivity type (p) is formed in said third well layer (nW3) at its surface and the value of a fourth voltage (VBB6) applied to said third well layer (nW3) is different from that of said first voltage.
Claim 4
Dependent Claim
270 words
A semiconductor device formed within a first region of a substrate (p-Sub) of a first conductivity type (p) comprising a first well layer (nW) of the second conductivity type (n) formed within said first region, a second well layer (pW1, pW2) of the first conductivity type (p) formed within said first well layer (nW), a first bipolar transistor npn3) having a first emitter and a first collector of said second conductivity type (n) and a first base of said first conductivity type (p), a second bipolar transistor (npn1, npn2) having a second emitter and a second collector of said second conductivity type (n) and a second base of said first conductivity type (p), wherein said first bipolar transistor (npn3) is formed in said first region at its surface and said second bipolar transistor (npn1, npn2) is formed in said second well layer (pW1, pW2) at its surface, wherein said first base is disposed in said first collector and wherein said first emitter is disposed in said first base, wherein said second base is disposed in said second collector and wherein said second emitter is disposed in said second base, first voltage means to apply a first voltage (VBB4) to said first well layer (nW), second voltage means to apply a second voltage (VBB2, VBB3) to said second well layer (pW1, pW2) and third voltage means to apply a third voltage (VBB1) to said first region, wherein the first voltage (VBB4) isolates the second well layer (pW1, pW2) and said first region, and wherein the value of said second voltage (VBB2, VBB3) is different from that of said third voltage (VBB1).
Claim 5
Dependent Claim
48 words
The semiconductor device according to claim 4, wherein a third bipolar transistor (pnp1) of the second type (pnp) having emitter and collector of said first conductivity type (p) and a base of said second conductivity type (n) is formed in the first well layer (nW) at its surface.
Claim 6
Dependent Claim
25 words
The semiconductor device according to any of claims 1 to 5, wherein said first conductivity type is p-type and said second conductivity type is n-type.
References Cited (Backward Citations)
JPS567463A
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.