EP0366882B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
An ultra dense DRAM cell array and its method of fabrication
Assignee: International Business Machines Corp
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Filing: 1989-08-02
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Granted: 1995-05-24
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Expires: 2009-08-02
Abstract
No abstract record available.
Inventors
- 👤 Daeje Chin
- 👤 Sang H. Dhong
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:55
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383; H10B12/30; H10B12/39; H10B12/395; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/242
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
384 words
A process for fabricating an ultra dense DRAM memory array containing a plurality of DRAM cells which process comprises the steps of: forming a first plurality of trenches (25) in a semiconductor substrate (21) which is spaced from an underlying - at least semiconductive - substrate (8) by an insulating layer (20), said trenches (25) extending through said semiconductor substrate (21) and said insulating layer (20) into said underlying substrate (8), refilling said plurality of trenches (25) with an insulating material (17), forming a second plurality of trenches (32) orthogonally intersecting said first plurality of trenches (25), said trenches (32) extending through said semiconductor substrate (21) and said insulating layer (20) into said underlying substrate (8) to a predetermined depth, said first and second plurality of trenches (25, 32), respectively, defining a plurality of upstanding semiconductor regions for forming the active device regions of the said DRAM cells and, when forming said second plurality of trenches (32), portions of said insulating material (17) filling said first plurality of trenches (25) being excavated at the intersections of said second plurality of trenches (32) with said first plurality of trenches (25) to a second depth having the level of gate conduits to be formed in a latter step, covering the trench walls of the second plurality of trenches (32) with insulation, refilling said second plurality of trenches (32) and said excavated portions of said first plurality of trenches (25) with a conductive material (11, 12), removing said conductive material from said excavated portions of said first plurality of trenches (25) to expose the surfaces of said insulating material (17′) therein and from alternating ones of said refilled second plurality of trenches (32) to a depth below said second depth to form a plurality of flat topped regions of said conductive (11) and said insulating materials which extend in a direction orthogonal to the direction of said first plurality of trenches (25), forming insulating regions (10) at the top of said plurality of flat topped regions of conductive material such that the tops of the resulting insulation regions (10) are at the same level as the tops of said flat topped regions of insulating material thereby forming a plurality of gate conduits extending in a direction orthogonal to the direction of said first plurality of trenches (25).
Claim 2
Dependent Claim
55 words
A process according to claim 1 wherein in said first semiconductor substrate (21) being of a first conductivity type a layer (22) of second conductivity type is provided extending from the surface of said first substrate (21) partially into said first substrate (21) and wherein said underlying substrate (8) is also of first conductivity type.
Claim 3
Dependent Claim
111 words
A process according to claim 1 or 2 further including the steps of forming a pair of gate conductors (6) in each of said gate conduits in insulated spaced relationship with adjacent of said upstanding semiconductor regions, depositing insulating material (15) in each of said gate conduits to electrically isolate the gate conductors (6) in each gate conduit from each other, introducing a conductivity determining dopant into the top part of said upstanding semiconductor regions to form doped device regions, planarizing said insulating material (15), and forming a plurality of conductors (16) disposed in orthogonal relationship with said gate conductors (6) each of said conductors (16) contacting said doped device regions.
Claim 4
Dependent Claim
68 words
A process according to any one of claims 1 to 3 wherein the step of forming the first plurality of insulation filled trenches includes the steps of: masking the said surface of said first semiconductor substrate (21) to expose portions of said surface, etching said substrate to form said plurality of trenches (25) and chemically vapor depositing said insulating material into said first plurality of insulation filled trenches.
Claim 5
Dependent Claim
167 words
A process according to any one of claims 1 to 4 wherein the step of forming the second plurality of trenches (32) and simultaneously excavating portions of said insulating material includes the steps of: forming layers of a nitride, oxide and a nitride in that order on said surface and over said insulation filled trenches (25), patterning said last mentioned nitride layer leaving spaced apart nitride masking regions, depositing a layer of polycrystalline semiconductor conformally over said spaced apart nitride regions and reactively ion etching said polycrystalline semiconductor to form sidewall spacers on the sides of each of said spaced apart nitride masking regions, removing said spaced apart masking regions, patterning said first mentioned nitride layer and said oxide layer to expose surface portions of said substrate (21) and said insulation filled trenches (25), and, reactively ion etching said exposed surface portion of said substrate (21) and said insulation filled trenches (25) to form said second plurality of trenches and excavated portions of said insulating material simultaneously.
Claim 6
Dependent Claim
127 words
A process according to anyone of claims 1 to 5 wherein the steps of covering the trench walls with insulation and refilling said trenches (32) and said excavated portions with conductive material (11, 12) includes the steps of: forming a composite oxide-nitride layer and a protective layer of polycrystalline semiconductor in said second plurality of trenches (32), subjecting said second plurality of trenches (32) to reactive ion etching to remove said protective layer of polycrystalline layer from said second plurality of trenches (32) and said composite oxide-nitride layer from the bottoms of said second plurality of trenches (32), depositing polycrystalline semiconductor material in said second plurality of trenches (32) and in said excavated portions and, polishing said semiconductor material to planarize the surface of said memory array.
Claim 7
Dependent Claim
59 words
A process according to any one of claims 1 to 6 wherein the step of removing said conductive material (11) from every other trench of said second plurality of trenches (32) filled with conductive material (11) includes the steps of: reactively ion etching said every other trench (32) to form a plurality of trenches in said conductive material (11).
Claim 8
Dependent Claim
38 words
A process according to claim 7 wherein the step of forming insulation at the bottom of each of said trenches in said conductive material (11) includes the step of oxidizing the topmost portion of said conductive material (11).
Claim 9
Dependent Claim
239 words
An ultra dense dynamic random access memory (DRAM) array containing a plurality of DRAM cells which array comprises: an at least semiconductive substrate (8, 11, 12) having a plurality of rows of DRAM cells (2) disposed in insulated spaced relationship with said substrate (8, 11, 12), said substrate having insulation regions (10) covering the top surfaces of substrate portions (11) which latter extend between pairs of DRAM cells (2) in each row and between insulation regions (17′), rows of which latter extend in the same direction as said rows of DRAM cells (2), the tops of said insulation regions (17′) being level with the tops of said insulation regions (10), a plurality of elongated gate conduits extending perpendicular to said rows of DRAM cells (2) and formed on said insulating regions (10) and on the surfaces of said insulating regions (17′), a pair of gate electrodes (6) disposed in each of said gate conduits and oriented therewith, each one of said pairs of gate electrodes being in insulated spaced relationship with the other one of said pair and with a portion (4) each of said DRAM cells (2) further having an extended region (5) disposed in insulated spaced relationship with said substrate and beneath said portion (4), and a plurality of conductive lines (16) disposed orthogonally with said gate electrodes (6), each of said conductive lines contacting another portion (3) of each DRAM cell (2) in the same row.
Claim 10
Dependent Claim
18 words
A dynamic random access memory array according to claim 9 wherein said DRAM cells are field effect transistors.
Claim 11
Dependent Claim
54 words
A dynamic random access memory array according to claim 9 or 10 wherein said portion (4) of said DRAM cell is the channel region of a field effect transistor, and wherein said region (5) and said another portion (3) of said DRAM cell are drain and source regions, respectively, of said field effect transistor.
References Cited (Backward Citations)
No citation records indexed.
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