EP0951072A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Hitachi Ltd
•
Filing: 1997-04-08
•
Granted: —
•
Expires: 2017-04-08
Abstract
Abstract The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel-current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period.
Inventors
- 👤 Nozomu Hitachi-daiyon-kyoshin-ryo MATSUZAKI
- 👤 Hiroyuki 87 Hitachi-koigakubo-ryo MIZUNO
- 👤 Masashi 207 39-2 Nakanoshima 6-chome HORIGUCHI
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:06
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/014; H10D84/0147; H10D84/0165; H10D84/0172; H10D84/0179; H10D84/0181; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/84; B; B82; B82Y; B82Y99/00; H10D84/0144; Y; Y10; Y10S; Y10S438/00; Y10S438/981; Y10S977/00; Y10S977/902; Y10S977/932; Y10S977/936
Claims Analysis
Total Claims: 63
Claim 1
Independent Claim
95 words
A semiconductor integrated circuit device
comprising on the same substrate a plurality of kinds
of metal oxide semiconductor (MOS) transistors
different in magnitude of leakage current flowing
either between the source and gate or between the
drain and gate, wherein said device has main circuitry
constituted from at least one MOS transistor of those
of said plurality of kinds of MOS transistors being
greater in leakage current, and control circuitry
inserted between said main circuitry and at least one
of two power supplies and comprised of at least one
MOS transistor less in leakage current.
Claim 2
Dependent Claim
18 words
The semiconductor integrated circuit device
according to Claim 1, wherein said leakage current is
due to tunnel current.
Claim 3
Dependent Claim
32 words
The semiconductor integrated circuit device
according to Claim 2, wherein said plurality of kinds
of MOS transistors different in said leakage current
include MOS transistors different in thickness of gate
insulation film.
Claim 4
Dependent Claim
35 words
The semiconductor integrated circuit device
according to any one of Claims 2 and 3, wherein said
MOS transistor greater in leakage current has a gate
insulation film of 3.5 nanometers (nm) or less in
thickness.
Claim 5
Dependent Claim
29 words
The semiconductor integrated circuit device
according to Claim 2 or 3, wherein the gate insulation
film of said MOS transistor greater in leakage current
is 3.0 nm or less.
Claim 6
Dependent Claim
29 words
The semiconductor integrated circuit device
according to Claim 2 or 3, wherein the gate insulation
film of said MOS transistor greater in leakage current
is 2.0 nm or less.
Claim 7
Dependent Claim
34 words
The semiconductor integrated circuit device
according to any one of Claims 2 to 6, wherein said
MOS transistor less in leakage current has a gate
insulation film of 5.0 nm or greater in thickness.
Claim 8
Dependent Claim
29 words
The semiconductor integrated circuit device
according to Claim 2 or 6, wherein the gate insulation
film of said MOS transistor less in leakage current is
10.0 nm or greater.
Claim 9
Dependent Claim
40 words
The semiconductor integrated circuit device
according to Claim 2, wherein said plurality of kinds
of MOS transistors different in said leakage current
include MOS transistors of the same conductivity type
having gate electrodes doped with an impurity of
different concentration.
Claim 10
Dependent Claim
32 words
The semiconductor integrated circuit device
according to Claim 2, wherein said plurality of kinds
of MOS transistors different in said leakage current
include MOS transistors different in density or
distribution of carrier.
Claim 11
Dependent Claim
24 words
The semiconductor integrated circuit device
according to any one of Claims 2 to 10, wherein said
main circuitry includes at least one logic circuit.
Claim 12
Dependent Claim
30 words
The semiconductor integrated circuit device
according to any one of Claims 2 to 11, wherein said
control circuitry includes at least one power supply
interruption transistor for power supply intercept.
Claim 13
Dependent Claim
36 words
The semiconductor integrated circuit device
according to Claim 21, further comprising a level hold
circuit for holding an output of said logic circuit or
said main circuitry when said power supply
interruption transistor intercepts power feed.
Claim 14
Dependent Claim
22 words
The semiconductor integrated circuit device
according to Claim 13, wherein said level hold circuit
comprises said MOS transistor less in leakage current.
Claim 15
Dependent Claim
36 words
The semiconductor integrated circuit device
according to any one of Claims 2 to 14, wherein said
MOS transistor greater in leakage current is arranged
to operate with a gate voltage of 0.8 volts (V) or
above.
Claim 16
Dependent Claim
35 words
The semiconductor integrated circuit device
according to any one of Claims 2 to 14, wherein said
MOS transistor greater in leakage current is arranged
to operate with a gate voltage of 1.2 V or higher.
Claim 17
Dependent Claim
41 words
The semiconductor integrated circuit device
according to any one of Claims 1 to 16, wherein said
MOS transistor greater in leakage current and said MOS
transistor less in leakage current are driven by gate
voltages different in potential from each other.
Claim 18
Dependent Claim
52 words
The semiconductor integrated circuit device
according to any one of Claims 1 to 16, wherein said
MOS transistor greater in leakage current is driven by
applying between the gate and one of the source and
drain a voltage less in potential than that applied to
said MOS transistor less in leakage current.
Claim 19
Dependent Claim
61 words
The semiconductor integrated circuit device
according to any one of Claims 1 to 18, further
comprising an input/output terminal, an input/output
circuit for control of input and output between said
input/output terminal and said main circuitry, a
memory cell for storage of an output of said main
circuitry, and a memory-direct peripheral circuit for
control of operation of said memory cell.
Claim 20
Dependent Claim
21 words
The semiconductor integrated circuit device
according to Claim 19, wherein said memory cell
comprises said MOS transistor less in leakage current.
Claim 21
Dependent Claim
32 words
The semiconductor integrated circuit device
according to Claim 19 or 20, wherein said memory cell
includes at least one of a register file, cash memory,
TBL, and dynamic random access memory (DRAM).
Claim 22
Dependent Claim
23 words
The semiconductor integrated circuit device
according to Claim 19 or 21, wherein said memory cell
is arranged to store data therein during standby.
Claim 23
Dependent Claim
67 words
The semiconductor integrated circuit device
according to any one of Claims 19 to 21, wherein said
memory cell includes a first type of memory greater in
access rate and a second type of memory less in access
rate than the first memory, and wherein leakage
current of a MOS transistor constituting said first
memory is greater than leakage current of a MOS
transistor constituting the second memory.
Claim 24
Dependent Claim
29 words
The semiconductor integrated circuit device
according to any one of Claims 19 to 23, wherein said
input/output circuit includes at least one current
interruption transistor for power supply interception.
Claim 25
Dependent Claim
29 words
The semiconductor integrated circuit device
according to any one of Claims 19-24, wherein said
memory-direct peripheral circuit includes at least one
power supply interruption transistor for power supply
interception.
Claim 26
Dependent Claim
48 words
The semiconductor integrated circuit device
according to Claim 23 or 24, further comprising a
power supply control circuit for control of said power
supply interruption transistor, wherein said power
supply interruption transistor comprises a MOS
transistor less in leakage current than the MOS
transistor constituting said main circuitry.
Claim 27
Dependent Claim
60 words
A semiconductor integrated circuit device
comprising a silicon substrate, a first MOS transistor
formed on said substrate and having an insulative film
of 4 nm thick or less between a source and gate or
between drain and gate, and a second MOS transistor
formed on the same substrate and measuring more than 4
nm in thickness of the insulative film.
Claim 28
Dependent Claim
86 words
A semiconductor integrated circuit device
comprising a first MOS transistor having between its
source and gate or between drain and gate an
insulative film of 4 nm or less in thickness, and a
second MOS transistor having between its source and
gate or between drain and gate an insulative film
greater in thickness than that of said first MOS
transistor, wherein said second MOS transistor
controls a current flowing between the source and gate
of said first MOS transistor or between the drain and
gate thereof.
Claim 29
Dependent Claim
60 words
A semiconductor integrated circuit device
comprising a first MOS transistor having between its
source and gate or between drain and gate an
insulative film of 4 nm or less, a second MOS
transistor for interruption of power feed to said
first MOS transistor, and level hold circuitry for
holding an output of said first MOS transistor during
power feed interruption.
Claim 30
Dependent Claim
74 words
A semiconductor integrated circuit device
comprising a first MOS transistor greater in magnitude
of leakage current between its source and gate or
between drain and gate, and a second MOS transistor
less in current leakage than said first MOS transistor,
wherein said first and second MOS transistors are on
the same silicon substrate, and wherein said second
MOS transistor is driven with a power supply
potentially higher than that for said first MOS
transistor.
Claim 31
Dependent Claim
88 words
A semiconductor integrated circuit device
responsive to receipt of an input signal with an
amplitude voltage Vcc2, said device comprising a level
converter circuit for generating an internal signal by
forcing the amplitude voltage of the input signal to
drop down at a potential level Vcc1, wherein a leakage
current between a gate and source or between gate and
drain of a MOS transistor receiving the internal
signal as its input is greater in magnitude than that
of a MOS transistor receiving said input signal as its
input.
Claim 32
Dependent Claim
76 words
A semiconductor integrated circuit device
comprising MOS transistors for provision of an
arithmetic processor device and a storage device
including at least one of a mask read-only memory,
static random access memory and dynamic random access
memory, wherein a gate insulation film of a MOS
transistor for use in a logic circuit included in said
arithmetic processor device is less in thickness than
a MOS transistor for use in a memory cell of said
storage device.
Claim 33
Dependent Claim
119 words
A semiconductor integrated circuit device
comprising a silicon substrate, a plurality of kinds
of MOS transistors on said substrate different in
magnitude of tunnel current between source and gate or
between drain and gate, main circuitry including at
least one MOS transistor greater in tunnel current of
said plurality of kinds of MOS transistors, and
control circuitry inserted between said main circuitry
and at least one of two power supplies and including
at least one MOS transistor less in tunnel current,
wherein flow of a source-to-gate current or drain-to-gate
current of the MOS transistor greater in tunnel
current for use in said main circuitry is selectively
permitted in response to a control signal as supplied
to said control circuitry.
Claim 34
Dependent Claim
95 words
A semiconductor integrated circuit device
comprising a semiconductive substrate, and a plurality
of kinds of MOS transistors on said substrate
different in thickness of a dielectric film laid
between a source and gate or between drain and gate,
wherein one or several ones of said plurality of kinds
of MOS transistors less in dielectric film thickness
are for use in constituting at least one logic circuit
whereas a remaining MOS transistor or transistors
greater in dielectric film thickness are for use in
forming a control circuit for control of power supply
to said logic circuit.
Claim 35
Dependent Claim
62 words
A semiconductor integrated circuit device
comprising a first MOS transistor having between its
source and gate or between drain and gate a dielectric
film of 4 nm or less in thickness, and a second MOS
transistor of more than 4 nm in thickness of the
dielectric film, wherein said second MOS transistor is
for controlling power supply to said first MOS
transistor.
Claim 36
Dependent Claim
153 words
A semiconductor integrated circuit device
comprising a semiconductor substrate, and a plurality
of kinds of MOS transistors on said substrate being
different in current leakage between source and drain
or between source and drain when driven by the same
gate voltage due to a difference in at least one of
thickness of a dielectric film laid between source and
gate or between drain and gate, density of gate
electrode carrier, and distribution thereof, wherein
said plurality of kinds of MOS transistors are for use
in constituting a central processing unit (CPU)
including at least one logic circuit, an input/output
circuit allowing a signal to input to and output from
said CPU, a memory circuit for storage of a signal
from said CPU, and wherein the MOS transistor less in
current leakage is for use with said logic circuit
whereas the MOS transistor greater in current leakage
is for use with said memory circuit.
Claim 37
Dependent Claim
146 words
A semiconductor integrated circuit device
comprising a semiconductor substrate, and a plurality
of kinds of MOS transistors on said substrate being
different in current leakage between source and drain
or between source and drain upon application of the
same voltage between a gate and one of drain and
source due to a difference in at least one of
thickness of a dielectric film laid between source and
gate or between drain and gate, density of gate
electrode carrier, and distribution thereof, wherein a
plurality of power supplies of different voltages are
provided to drive said plurality of MOS transistors,
and wherein one or several first MOS transistors
greater in current leakage of said plurality of kinds
of MOS transistors are driven with a first power
supply of lower voltage whereas one or several second
MOS transistors are driven with a second power supply
of higher voltage.
Claim 38
Dependent Claim
119 words
A semiconductor integrated circuit device
comprising on the same semiconductive substrate a
plurality of kinds of MOS transistors different in
current leakage between source and gate or between
source and drain when driven by the same gate voltage,
a plurality of power supplies different in voltage for
driving the plurality of MOS transistors, wherein one
or more first MOS transistors greater in current
leakage of said plurality of kinds of MOS transistors
are driven by a first power supply of low voltage
whereas one or more second MOS transistors less in
current leakage thereof are driven by a second power
supply of high voltage while allowing said second MOS
transistors to control power supply to said first MOS
transistors.
Claim 39
Dependent Claim
77 words
A semiconductor integrated circuit device
comprising on the same semiconductor substrate a first
MOS transistor greater in current leakage between its
source and gate or between source and drain, and a
second MOS transistor less in current leakage, wherein
said first MOS transistor is for use in constituting a
first circuit whereas said second MOS transistor is
for use in forming a second circuit while rendering
said first circuit greater in switching speed than
said second circuit.
Claim 40
Dependent Claim
96 words
A semiconductor integrated circuit device
comprising a first MOS transistor having a thickness
decreased insulative film between its source and gate
or between source and drain, and a second MOS
transistor having a thickness increased insulative
film, wherein said first MOS transistor is for use
with a logic circuit required to exhibit enhanced
switching speed whereas said second transistor is for
use with a circuit less in switching speed than said
logic circuit while allowing a power supply of said
first MOS transistor to be controlled independently of
a power supply of said second MOS transistor.
Claim 41
Dependent Claim
126 words
A semiconductor integrated circuit device
comprising a first MOS transistor having a first gate
electrode, a first electrode and a second electrode,
and a second MOS transistor with a second gate
electrode, a third electrode and a fourth electrode,
wherein said first electrode is coupled to a first
potential whereas said second electrode is coupled to
a second potential, wherein said second MOS transistor
is inserted via said third electrode and said fourth
electrode at at least one of certain locations one of
which is between said first electrode and said first
potential and a remaining one of which is between said
second electrode and said second potential, and
wherein said first MOS transistor is less in gate
insulation film thickness than said second MOS
transistor.
Claim 42
Dependent Claim
24 words
The semiconductor integrated circuit device
according to Claim 41, wherein said first MOS
transistor is less in gate length than said second MOS
transistor.
Claim 43
Dependent Claim
24 words
The semiconductor integrated circuit device
according to Claim 41, wherein said first MOS
transistor is less in gate voltage than said second
MOS transistor.
Claim 44
Dependent Claim
25 words
The semiconductor integrated circuit device
according to Claim 41, wherein said first MOS
transistor is less than or equal to 2 volts in gate
voltage.
Claim 45
Dependent Claim
39 words
The semiconductor integrated circuit device
according to Claim 41, wherein said first MOS
transistor is less than 4 nm in gate insulation film
thickness whereas said second MOS transistor is
greater than 4 nm in gate insulation film thickness.
Claim 46
Dependent Claim
24 words
The semiconductor integrated circuit device
according to Claim 41, wherein said first MOS
transistor is less than 3.5 nm in gate insulation film
thickness.
Claim 47
Dependent Claim
24 words
The semiconductor integrated circuit device
according to Claim 41, wherein said first MOS
transistor is less than 3 nm in gate insulation film
thickness.
Claim 48
Dependent Claim
24 words
The semiconductor integrated circuit device
according to Claim 41, wherein said first MOS
transistor is less than 2 nm in gate insulation film
thickness.
Claim 49
Dependent Claim
24 words
The semiconductor integrated circuit device
according to Claim 41, wherein said second MOS
transistor is greater than 5 nm in gate insulation
film thickness.
Claim 50
Dependent Claim
24 words
The semiconductor integrated circuit device
according to Claim 41, wherein said second MOS
transistor is greater than 6 nm in gate insulation
film thickness.
Claim 51
Dependent Claim
24 words
The semiconductor integrated circuit device
according to Claim 41, wherein said second MOS
transistor is greater than 10 nm in gate insulation
film thickness.
Claim 52
Dependent Claim
110 words
A semiconductor integrated circuit device
comprising on the same silicon substrate a plurality
of kinds of MOS transistors different in magnitude of
tunnel current flowing at least between source and
gate or between drain and gate, a main circuit
configured including at least one MOS transistor
greater in tunnel current of said plurality of kinds
of MOS transistors different in magnitude of tunnel
current, a control circuit inserted between said main
circuit and at least one of two power supplies for
controlling current flow between the source and gate
or between the drain and gate of the MOS transistor
greater in tunnel current for use in constituting said
main circuit.
Claim 53
Dependent Claim
32 words
The semiconductor integrated circuit device
according to Claim 52, wherein said plurality of kinds
of MOS transistors different in magnitude of tunnel
current comprise MOS transistors different in gate
insulation film thickness.
Claim 54
Dependent Claim
60 words
The semiconductor integrated circuit device
according to Claim 53, wherein said plurality of kinds
of MOS transistors different in magnitude of tunnel
current include a MOS transistor having a thickness-increased
gate insulation film and a gate electrode
side wall with a side wall spacer being coated thereon,
said spacer being made of a dielectric material
substantially insensitive to hydrofluoric acid.
Claim 55
Dependent Claim
45 words
The semiconductor integrated circuit device
according to Claim 52, wherein said plurality of kinds
of MOS transistors different in magnitude of tunnel
current comprise MOS transistors identical in
conductivity type having gate electrodes doped with
the same kind of impurity at different values of
concentration.
Claim 56
Independent Claim
41 words
A method of manufacturing a semiconductor
device for fabrication of a plurality of metal oxide
semiconductor (MOS) transistors having gate insulation
films different in thickness on the same silicon
substrate, wherein the gate insulation films of
different thicknesses are formed separately.
Claim 57
Independent Claim
48 words
A method of manufacturing a semiconductor
device for fabrication of a plurality of MOS
transistors having gate insulation films different in
thickness on the same silicon substrate, wherein a
gate insulation film less in thickness is formed prior
to formation of a gate insulation film greater in
thickness.
Claim 58
Independent Claim
114 words
A method of manufacturing a semiconductor
device comprising on the same silicon substrate a
plurality of MOS transistors each having a lamination
of a gate insulation film and a gate electrode, said
plurality of MOS transistors including a first MOS
transistor and a second MOS transistor different from
each other in thickness of the gate insulation film,
said method comprising the steps of: forming the gate insulation film of said first MOS
transistor to a thickness less than that of said
second MOS transistor; forming the gate insulation film and the gate
electrode of said second MOS transistor; and forming thereafter the gate insulation film and
the gate electrode of said first MOS transistor.
Claim 59
Dependent Claim
90 words
A semiconductor integrated circuit device
comprising on the same silicon substrate a first MOS
transistor having a first gate insulation film of a
predefined thickness, and a second MOS transistor
having a second gate insulation film greater in
thickness than said first gate insulation film,
wherein said second MOS transistor includes a source
electrode and a drain electrode while letting at least
one of the source and drain electrodes comprise an
impurity-doped region different in carrier density or
in depth from a corresponding one electrode of said
first MOS transistor.
Claim 60
Dependent Claim
117 words
A semiconductor integrated circuit device
comprising on the same silicon substrate a first MOS
transistor having a first gate insulation film, a
first gate electrode overlying said film, and a first
protective dielectric film overlying said gate
electrode, a second MOS transistor having a second
gate insulation film, a second gate electrode
overlying the second film, and a second protective
dielectric film overlying said second gate electrode,
wherein said first gate insulation film is less in
thickness than said second gate insulation film, and
wherein a side wall dielectric film is provided at
least partly covering a cross-section of said second
gate insulation film and said second gate electrode as
well as said second protective dielectric film.
Claim 61
Dependent Claim
169 words
A semiconductor integrated circuit device
comprising on the same silicon substrate a first MOS
transistor with a first gate insulation film, a first
gate electrode overlying said film, and a first
protective dielectric film overlying said gate
electrode, a second MOS transistor with a second gate
insulation film, a second gate electrode overlying the
second film, and a second protective dielectric film
overlying said second gate electrode, wherein said
first gate insulation film is less in thickness than
said second gate insulation film, wherein a side wall
dielectric film is provided at least partly covering a
cross-section of said second gate insulation film and
said second gate electrode as well as said second
protective dielectric film, and further comprising a
first impurity-doped region in said silicon substrate
beneath said side wall dielectric film, and a second
impurity-doped region in certain part of said silicon
substrate neighboring to said side wall dielectric
film, said second impurity-doped region being
prevented from locating beneath the side wall and the
gate insulation film.
Claim 62
Dependent Claim
101 words
A semiconductor integrated circuit device
comprising on the same silicon substrate a plurality
of MOS transistors of a first kind each having between
its source and gate or between drain and gate an
insulative film of 4 nm or less in thickness, a
plurality of MOS transistors of a second kind being
greater than 4 nm in thickness of the insulative film,
wherein the first kind of MOS transistors include a
MOS transistor with a maximal gate length while the
second kind of MOS transistors include a MOS
transistor with a minimal gate length being greater
than said maximal gate length.
Claim 63
Dependent Claim
98 words
A semiconductor integrated circuit device
comprising on the same silicon substrate a first MOS
transistor having a first gate insulation film, a
first gate electrode overlying said film, and a first
protective dielectric film overlying said gate
electrode, a second MOS transistor having a second
gate insulation film, a second gate electrode
overlying the second film, and a second protective
dielectric film overlying said second gate electrode,
wherein said first gate insulation film is less in
thickness than said second gate insulation film, and
wherein said first gate insulation film is thinner
than said second gate insulation film.
References Cited (Backward Citations)
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