Dynamic RAM

Claim 1

A dynamic RAM comprising: a semiconductor substrate; a plurality of semiconductor pillar projections separated by grooves formed in longitudinal and transverse directions in said semiconductor substrate, said semiconductor pillar projections being arranged in a matrix manner; a plurality of MOS capacitors formed on side surfaces at a lower portion of each of said semiconductor pillar projections, said each MOS capacitor including, a memory node formed in side surface at the lower portion of each semiconductor pillar projection, a capacitor insulating film formed on the side surface at the lower portion of each semiconductor pillar projection, and a capacitor electrode formed on said capacitor insulating film; a plurality of MOSFETs formed on side surfaces at an upper portion of each semiconductor pillar projection, said each MOSFET including, a channel region formed at least on the side surface at the upper portion of each semiconductor pillar projection, source and drain regions formed above and below said channel region to sandwich said channel region, a gate insulating film formed on the side surface at the upper portion of each semiconductor pillar projection in which said channel region is formed, and a gate electrode formed on said gate insulating film; a plurality of bit line contacts each contact formed on an upper surface of a corresponding semiconductor pillar projection; and a plurality of bit lines each bit line connected to associated bit line contacts; characterized in that said plurality of semiconductor pillar projections is divided into a plurality of blocks, each block having at least one contact semiconductor pillar projection comprising a first insulating layer which is thicker than said gate insulating film of said MOSFET and is formed on an upper surface of said contact semiconductor pillar projection, and a word line contact pad formed on said first insulating layer, said contact pad being electrically connected to said gate electrode of memory cells in each block.