EP0642173A1
Expired / Lapsed
EP
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Semiconductor element and semiconductor memory device using the same
Assignee: Hitachi Ltd
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Filing: 1994-08-12
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Granted: —
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Expires: 2014-08-12
Abstract
Abstract A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance (C gc ) is set so small that whether or not a trap (7) captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.
Inventors
- 👤 Kazuo Yano
- 👤 Tomoyuki Ishii
- 👤 Takashi Hashimoto
- 👤 Koichi Seki
- 👤 Masakazu Aoki
- 👤 Takeshi La Kabina De Amichi 301 Sakata
- 👤 Yoshinobu Nakagome
- 👤 Kan Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 03:23
CPC Classifications
H; H10; H10B; H10B12/00; B; B82; B82Y; B82Y10/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/06; G11C16/10; G11C16/26; G11C16/28; H10B41/00; H10B41/20; H10B41/40; H10B41/42; H10B41/49; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/40; H10D30/402; H10D30/60; H10D30/68; H10D30/688; H10D30/6891; H10D30/6892; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; G11C2216/00; G11C2216/02; G11C2216/06; G11C2216/08; H10D30/62; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
189 words
A semiconductor element, comprising: a source region (1, 19, 35) constituting a source of said semiconductor element; a drain region (2, 20, 36) constituting a drain of said semiconductor element; an effective channel region (3, 21, 33, 39, 46) provided between said source region (1, 19, 35) and said drain region (2, 20, 36) for interconnection thereof; a gate electrode (4, 22, 31; 32, 37; 38) connected to said effective channel region (3, 21, 33, 39) through a gate insulation film (5, 23, 40, 49; 50; 53) interposed between said gate electrode and said effective channel region; and a level node (7, 24, 34, 47)formed between said source region and said drain region in the vicinity of a current path (6) in said effective channel region for capturing at least one carrier, wherein effective capacitance between said gate electrode and said effective channel region is set so small as to satisfy a condition given by the following inequality expression: 1/C gc > kT/q² where C gc represents said effective capacitance, k represents Boltzmann's constant, T represents an operating temperature in degree Kelvin, and q represents charge of an electron.
Claim 2
Dependent Claim
74 words
A semiconductor element according to claim 1, wherein when a potential difference between said gate electrode (4, 22, 31; 32, 37; 38) and said source (1, 19, 35) is increased and decreased repetitively while holding constant a voltage between said drain (2, 20, 36) and said source (1, 19, 35), conductance between said gate electrode (4, 22, 31; 32, 37; 38) and said source (1, 19, 35) exhibits a hysteresis at a room temperature.
Claim 3
Dependent Claim
23 words
A semiconductor element according to claim 1, wherein said effective channel region (3, 21, 33, 39, 46) is formed of a polycrystalline semiconductor.
Claim 4
Dependent Claim
23 words
A semiconductor element according to claim 2, wherein said effective channel region (3, 21, 33, 39, 46) is formed of a polycrystalline silicon.
Claim 5
Dependent Claim
44 words
A semiconductor element according to claim 1, wherein said effective capacitance (C gc ) between said gate electrode (4, 22, 31; 32, 37; 38) and said effective channel region (3, 21, 33, 39, 46) is set at a value not greater than 6 aF.
Claim 6
Dependent Claim
37 words
A semiconductor memory device, comprising: a plurality of semiconductor elements (MPn) each of a structure set forth in claim 1, wherein said plurality of semiconductor elements (MPn) are controlled via word wires (W) and data wires (D).
Claim 7
Dependent Claim
208 words
A semiconductor memory device according to claim 6, wherein when a potential difference between said gate electrode (4, 22, 31; 32, 37; 38) and said source (1, 19, 35) or said drain (2, 20, 36) of said semiconductor element is represented by V gs , said potential difference (V gs ) is set to a voltage (V g1 ) for writing logic "1" to thereby rise a threshold voltage of a selected one of said plural semiconductor elements (MPn, MMn), and said potential difference (V gs ) of said selected semiconductor element is externally set to a voltage (V g0 ) for writing logic "0" which is lower than said logic "1" writing voltage (V g1 ) to thereby lower the threshold voltage of said semiconductor element, and wherein a potential difference (V gs ) between said logic "1" writing voltage (V g1 ) and said logic "0" writing voltage (V g0 ) is applied to said selected semiconductor element (PM, MM) as said potential difference V gs with a potential difference being additionally applied to said selected semiconductor element between said source (1, 19, 35) and said drain (2, 20, 36) thereof, to thereby read out information by detecting a drain-source current of said selected semiconductor element.
Claim 8
Dependent Claim
67 words
A semiconductor memory device according to claim 7, wherein a circuit for controlling rising or lowering of said threshold voltage and a circuit for detecting said current are constituted by field-effect transistors (FETs) formed in a surface area of a monocrystalline semiconductor substrate (14), and wherein said plurality of said semiconductor elements (MPn, MMn) are formed on said circuits (FETs) with an insulation film being interposed therebetween.
Claim 9
Dependent Claim
73 words
A semiconductor element according to claim 1, said effective channel region (3, 21, 33, 39, 46) and said source region (1, 19, 35) being each formed by a semiconductor thin film, wherein a portion of said source region (1, 19, 35) at which said source region (1, 19, 35) is to be connected to a wire has a film thickness greater than that of said effective channel region (3, 21, 33, 39, 46).
Claim 10
Dependent Claim
41 words
A semiconductor element according to claim 1, wherein periphery of said effective channel region (3, 21, 33, 39, 46) is covered with a material having a dielectric constant smaller than that of said effective channel region (3, 21, 33, 39, 46).
Claim 11
Dependent Claim
176 words
A semiconductor element, comprising: a source region (19) constituting a source of said semiconductor element; a drain region (20) constituting a drain of said semiconductor element; said source region (19) being connected to said drain region (20) through an effective channel region (21) interposed therebetween; a gate electrode (22) connected to said effective channel region (21) through a gate insulation film (23, 25) interposed between said gate electrode (22) and said effective channel region (21); at least one carrier confinement region (24) formed in the vicinity of said effective channel region (21) for confining a carrier; and a potential barrier (25) existing between said carrier confinement region (24) and said effective channel region (21); wherein effective capacitance (C gc ) between said gate electrode (22) and said effective channel region (21) is set so small as to satisfy a condition given by the following inequality expression: 1/C gc > kT/q² where C gc represents said effective capacitance, k represents Boltzmann's constant, T represents an operating temperature in degree Kelvin, and q represents charge of an electron.
Claim 12
Dependent Claim
204 words
A semiconductor element, comprising: a source region (19) constituting a source of said semiconductor element; a drain region constituting a drain (20) of said semiconductor element; said source region (19) being connected to said drain region (20) through an effective channel region (21) interposed therebetween; a gate electrode (22) connected to said effective channel region (21) through a gate insulation film (23) interposed between said gate electrode (22) and said effective channel region (21); at least one carrier confinement region (24) formed in the vicinity of said effective channel region (21) for confining a carrier; and a potential barrier (25) existing between said carrier confinement region (24) and said effective channel region (21); wherein a value of capacitance between said effective channel region (21) and said carrier confinement region (24) is set greater than capacitance between said gate electrode (22) and said carrier confinement region (24); and wherein total capacitance (C tt ) existing around said carrier confinement region (24) is so set as to satisfy a condition given by the following inequality expression: q²/2C tt > kT where C tt represents said total capacitance, k represents Boltzmann's constant, T represents an operating temperature in degree Kelvin, and q represents charge of an electron.
Claim 13
Dependent Claim
43 words
A semiconductor element according to claim 12, wherein effective capacitance (C gc ) between said gate electrode (22) and said effective channel region (21) is set so small as to satisfy a condition given by the following inequality expression: 1/C gc > T/q².
Claim 14
Dependent Claim
22 words
A semiconductor element according to claim 11 or 12, wherein said effective channel region (21) is provided on an insulation film (25).
Claim 15
Dependent Claim
50 words
A semiconductor element according to claim 11 or 12, said gate electrode including a first gate electrode (31) and a second gate electrode (32), wherein said effective channel region (33) and said carrier confinement region (34) are disposed between said first gate electrode (31) and said second gate electrode (32).
Claim 16
Dependent Claim
44 words
A semiconductor element according to claim 11 or 12, said gate electrode including a first gate electrode (37) and a second gate electrode (38), wherein said second gate electrode (38) is disposed between said first gate electrode (37) and said effective channel region (39).
Claim 17
Dependent Claim
24 words
A semiconductor element according to claim 11 or 12, wherein an island of crystal thin film is used for forming said carrier confinement region.
Claim 18
Dependent Claim
161 words
A semiconductor element, comprising: a source region (19) constituting a source of said semiconductor element; a drain region (20) constituting a drain of said semiconductor element; said source region being connected to said drain region through an effective channel region (46) interposed therebetween; a gate electrode (51) connected to said effective channel region (46) through a gate insulation film (49, 50) interposed between said gate electrode (51) and said effective channel region (46); at least one carrier confinement region (47) formed in the vicinity of said effective channel region (46) for confining a carrier, said confinement region (47) being surrounded by a potential barrier (23, 25; 50; 53); storage of information being effectuated by holding carrier in said carrier confinement region (24, 47); and a thin film structure (48) having a thickness not greater than 9 nm and formed of a semiconductor material in an insulation film (50) intervening between said effective channel region (46) and said carrier confinement region (47).
Claim 19
Dependent Claim
87 words
A semiconductor memory device, comprising: a plurality of memory cells (MMn) each including a semiconductor element set forth in any one of claims 1, 11, 12, and 18. wherein said gate electrode of each of said semiconductor elements is connected to a word wire (W); a source-drain path of each of said semiconductor elements being connected between a data wire (D) and an operating potential point (P); and wherein said plurality of memory cells (MMn) are controlled via said word wires (W) and said data wires (D).
Claim 20
Dependent Claim
59 words
A semiconductor memory device, comprising: a plurality of memory cells each including a semiconductor element set forth in any one of claims 1, 11, 12 and 18, wherein said gate electrode is connected to said drain; and wherein a source-drain path of each of said semiconductor elements is connected between a word wire (W) and a data wire (D).
Claim 21
Dependent Claim
99 words
A semiconductor memory device, comprising: a plurality of memory cells each including a switching element (M25) and a semiconductor element set forth in any one of claims 1, 11, 12 and 18; wherein a source-drain path of each of said switching elements (M25) is connected in series to each of said semiconductor elements between a data wire (D) and an operating potential point (P); gate of each of said switching elements (M25) being controlled via a word wire (W); whereby each of said memory cells (MM81, MM82) is controlled via said word wire (W) and said data wire (D).
Claim 22
Dependent Claim
156 words
A semiconductor memory device, comprising: a plurality of memory cells each of which includes; a first semiconductor element (MM31) set forth in any one of claims 1, 11, 12 and 18 and having a source-drain path connected between a first operating potential point (C) and a first node (N31); a second semiconductor element (MM32) set forth in claim 1 and having a source-drain path connected between said first node (N31) and a second operating potential point (P); wherein each of said memory cells stores as data of logic "1" a state in which a threshold voltage of said first semiconductor element (MM31) is low while a threshold voltage of said second semiconductor element (MM32) is high; and wherein each of said memory cells stores as data of logic "0" a state in which the threshold voltage of said first semiconductor element (MM31) is high while the threshold voltage of said second semiconductor element (MM32) is low.
Claim 23
Dependent Claim
164 words
A semiconductor memory device, comprising: a plurality of memory cells each of which includes; a first semiconductor element (MM41) set forth in any one of claims 1, 11, 12 and 18 and having a source-drain path connected between a first data wire (D) and an operating potential point (P); and a second semiconductor element (MM42) set forth in any one of claims 1, 11, 12 and 18 and having a source-drain path connected between a second data wire (Dn) and the operating potential point (P); wherein each of said memory cells stores as data of logic "1" a state in which a threshold voltage of said first semiconductor element (MM41) is low while a threshold voltage of said second semiconductor element (MM42) is high; and wherein each of said memory cells stores as data of logic "0" a state in which the threshold voltage of said first semiconductor element (MM41) is high while the threshold voltage of said second semiconductor element (MM42) is low.
Claim 24
Dependent Claim
84 words
A semiconductor memory device according to claim 23, wherein each of said memory cells further includes first and second switching elements (M45, M46), said first switching element (M45) having a source-drain path connected in series to said first semiconductor element (MM41) between said first data wire (D) and said operating potential point (P); and said second switching element (M46) having a source-drain path connected in series to said second semiconductor element (MM42) between said second data wire (Dn) and said operating potential point (P).
Claim 25
Dependent Claim
147 words
A semiconductor memory device, comprising: a plurality of memory cells each including a first semiconductor element (MM51) set forth in any one of claims 1, 11, 12 and 18 and having a source-drain path connected between a first data wire (MD51) and an operating potential point; a plurality of dummy cells each including a second semiconductor element (MM54) set forth in any one of claims 1, 11, 12 and 18 and having a source-drain path connected between a second data wire (MD52) and said operating potential point; and a differential amplifier (MA51); wherein a signal on said first data wire (MD51) drives a first input terminal of said differential amplifier, while a signal on said second data wire (MD52) drives a second input terminal of said differential amplifier; and wherein data is read out from said memory cell by reading an output signal of said differential amplifier.
Claim 26
Dependent Claim
106 words
A semiconductor memory device according to claim 25, a first amplifier circuit (PA51) connected to said first data wire (D); a first main data wire (MD51) to which output of said first amplifier circuit (PA51) is connected; said first input terminal of said differential amplifier (MA51) being driven by a signal on said first main data line (MD51); a second amplifier circuit (PA52) connected to said second data wire; and a second main data wire (MD52) to which output of said second amplifier (PA52) is connected; said second input terminal of said differential amplifier (MA51) being driven by a signal on said second main data wire.
Claim 27
Dependent Claim
36 words
A semiconductor memory device according to claim 26, wherein said second amplifier circuit (PA52) is so designed as to have an output current driving capability which is smaller than that of said first amplifier circuit (PA51).
Claim 28
Dependent Claim
117 words
A semiconductor memory device, comprising: first and second semiconductor elements each of a structure set forth in any one of claims 1, 11, 12 and 22, each of said first and second semiconductor elements (MM70) including an electrically conducting (B) region located in the vicinity of said channel in addition to said gate electrode; the conducting region (B) of said first semiconductor element (MM70) and that of said second semiconductor element (MM70) being in a mutually conductive state; wherein positional relationship between said conducting regions and said effective channel region is so set that potentials of channels of said first and second semiconductor elements can change simultaneously in response to change in potential of said conducting region.
Claim 29
Dependent Claim
109 words
A semiconductor memory device, comprising: a plurality of memories each cell including a semiconductor element set forth in any one of claims 1, 11, 12 and 22 and having a source-drain path connected between a data wire (D) and an operating potential level (P); an amplifier having an input terminal driven by a signal on said data wire (D); wherein data of said memory cell is read out by reading an output signal from said amplifier; and wherein after said data reading, rewriting operation is performed for said memory cell by generating a predetermined writing voltage on said data wire in dependence on the output signal of said amplifier.
Claim 30
Dependent Claim
34 words
A data processing apparatus, comprising a processor and a storage, said storage including a nonvolatile semiconductor memory device which comprises a plurality of semiconductor elements each of a structure set forth in claim 6.
Claim 31
Dependent Claim
138 words
A semiconductor memory element, comprising: a source region (1) and a drain region (2) each formed of a semiconductor material; an effective channel region (3) formed of a semiconductor material and provided between said source region and said drain region; a gate electrode (4) contacted to said effective channel region through a gate insulation film (5) interposed therebetween; and a trap (7) formed in said effective channel region in the vicinity of a current path (6) extending between said source region and said drain region for capturing at least one carrier; wherein said trap (7) is located within said effective channel region at a position so close to said current path that an electric field effect is exerted onto said current path by said trap, and wherein said current path has a thickness of 10 nm at maximum.
Claim 32
Dependent Claim
58 words
A semiconductor memory element according to claim 31, wherein effective capacitance between said gate electrode and said effective channel region satisfies condition given by the following inequality expression: 1/C gc > kT/q² where C gc represents said effective capacitance, k represents Boltzmann's constant, T represents an operating temperature in degree Kelvin, and q represents charge of an electron.
Claim 33
Dependent Claim
38 words
A semiconductor memory element according to claim 31, wherein said effective channel region is formed of a polycrystalline semiconductor material in a thickness not greater than 100 nm, and said trap is formed by a crystal grain boundary.
References Cited (Backward Citations)
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