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JPH08213624A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device and operating method thereof

Assignee: Fujitsu Ltd
•
Filing: 1995-02-08
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Granted: —
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Expires: 2015-02-08
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Abstract

Abstract Translated from Japanese (57)【要約】 【目的】 半導体記憶装置及びその動作方法に関し、電 荷の保持時間を長くし、且つ、消去時間を大幅に短縮 し、さらに、多値記憶を可能にする。 【構成】 支持基板1上に絶縁膜2を介して設けられ、 且つ、隣接する領域から完全に電気的に絶縁分離された 厚さ0.1μm以上の複数の半導体島状領域3に夫々1 つのMISFETを設け、且つ、MISFETのソース ・ドレイン領域7,8とは反対導電型の電荷からなるデ ータ記憶のための電荷12をMISFETのソース・ド レイン領域間の電気的に浮遊した領域11に蓄積する。 (57) [Summary] [Object] A semiconductor memory device and an operation method thereof, in which an electric charge holding time is lengthened, an erasing time is significantly shortened, and further, multi-value storage is enabled. [Structure] Provided on a supporting substrate 1 via an insulating film 2, In addition, a plurality of semiconductor island regions 3 each having a thickness of 0.1 μm or more, which are completely electrically insulated from the adjacent regions, are provided in each of the semiconductor island regions 3. Two MISFETs are provided, and a charge 12 for storing data, which is a charge of a conductivity type opposite to that of the source / drain regions 7 and 8 of the MISFET, is accumulated in an electrically floating region 11 between the source / drain regions of the MISFET. To do.

Inventors

  • 👤 Takao Miura
  • 👤 隆雄 三浦

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 08:56
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/711; H10B; H10B12/00; H10B12/20

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