Semiconductor memory device

Claim 1

A semiconductor memory device comprising: a peripheral circuit composed of a field effect transistor (34d, 34s, 36) formed in a semiconductor substrate (31) of a first conductivity type and a memory cell composed of a field effect transistor (4s, 4c, 4d) and a capacitor (3b, 4, 32), formed in a well region (32) of second conductivity type, opposite the first conductivity type, in a surface portion of the semiconductor substrate (31); an insulating layer having a thin portion (3b) and a thick portion (41) formed on the well region (32); a semiconductor layer (4) formed on the insulating layer (41, 42); and the memory cell field effect transistor (4s, 4c, 4d) being formed in the semiconductor layer (4); and, the memory cell capacitor having its dielectric formed by the thin portion (3b) of the insulating layer, an upper electrode of the second conductivity type formed by a portion of the semiconductor layer (4), and a lower electrode formed by the well portion (32); the well portion being arranged to be biased with a voltage at an intermediate level between a first storage voltage and a second storage voltage applied to the semiconductor layer, thereby reducing the field strength across the dielectric of the memory cell capacitor.