EP0362961B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A method of operating a MOS-structure and MOS-structure therefor
Assignee: Imec
•
Filing: 1989-10-03
•
Granted: 1994-02-16
•
Expires: 2009-10-03
Abstract
Abstract A SOI-nMOS-structure is cooled such that a charge is maintained in a cavity (5) of such structure for a long period of time. Applications comprise memory element.
Inventors
- 👤 Marnix Roger Anna Tack
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:54
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/387; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
116 words
A method of operating a SOI-FET-structure, including a conducting back gate (2), a back oxide (3) provided thereon, a silicon film (4) provided thereon of one conductivity type provided with a channel region (5) in which semiconductor material of the other conductivity type is provided, an oxide layer (6) provided on said region of the other conductivity type, and a conducting top gate (7) provided on said oxide layer, characterized by influencing the amount of charge in the channel region such that the threshold voltage of said FET is adjusted and maintaining such channel charge condition during a certain time period by cooling the SOI-FET-structure such that a multistable operating condition of said FET is obtained.
Claim 2
Dependent Claim
22 words
A method according to claim 1, in which the charge is supplied by a voltage, preferably a pulse, to the back gate.
Claim 3
Dependent Claim
18 words
A method of claim 1 and 2, in which the voltage to the back gate comprises a pulse.
Claim 4
Dependent Claim
42 words
A method of claim 1, 2 or 3, comprising the step of cooling the SOI-FET-structure at a value below room temperature, preferably below 300 K, more preferably at approx. 77 K, on around 4 K or between 4 K and 77 K.
Claim 5
Independent Claim
62 words
A method according to one of the claims 1-4, in which the SOI-FET-structure comprises one or more NMOS-transistors, a DC voltage of -20 Volt being supplied to the back gate, a pulse to 0 Volt, or -40 Volt being superimposed to the DC voltage and in which to the front gate and/or back gate pulses drain to e.g. 5 Volt are supplied.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.