EP0350057B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory
Assignee: Toshiba Corp
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Filing: 1989-07-07
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Granted: 1993-12-01
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Expires: 2009-07-07
Abstract
No abstract record available.
Inventors
- 👤 Tohru Intellectual Property Division K.K Furuyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:10
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
94 words
A semiconductor memory comprising: a bit line and a word line; a memory cell including a capacitor element, and a MOS transistor, one current path of which is connected to said capacitor, the other current path of which is connected to said bit line, and a gate electrode of which is connected to said word line; and a substrate potential line connected to a back gate of said MOS transistor; characterized by a potential switching device, connected to said substrate potential line, for controlling a potential of said back gate of said MOS transistor.
Claim 2
Dependent Claim
50 words
A memory according to claim 1, characterized in that said potential switching device controls the potential of said back gate of said MOS transistor at every predetermined period of time so that said MOS transistor becomes an enhancement type or a depletion type which can prevent a threshold voltage loss.
Claim 3
Dependent Claim
100 words
A memory according to claim 1, characterized in that said memory cell comprises a well region of a second conductivity type formed in a semiconductor substrate of a first conductivity type, said MOS transistor being of a first channel type and formed on a surface of said well region, a third impurity layer for electric charge storage of the first conductivity type formed on the surface of said well region to be in contact with a first or second impurity layer of said MOS transistor, and a capacitor electrode disposed on said third impurity layer through a capacitor insulating film.
Claim 4
Dependent Claim
124 words
A memory according to claim 1, characterized in that said memory cell comprises a semiconductor region (53) of a second conductivity type formed in a insulating layer (52) which is formed on a semiconductor substrate (51), said MOS transistor (T) being of a first channel type and formed on a surface of said semiconductor region (53), a third impurity layer for storing electrical charge, said third impurity layer being of the first conductivity type and formed on a surface of said insulating layer (52) by stretching either a first or second impurity layer (54, 55) of said MOS transistor into said insulating layer (52), and a capacitor electrode (58) formed on a capacitor insulating film (57) which is formed on said third impurity layer.
Claim 5
Dependent Claim
24 words
A memory according to claim 1, characterized in that potential switching device (Vbb) is controlled by timing pulses for selecting said word line (WL).
Claim 6
Dependent Claim
25 words
A memory according to claim, 2 characterized in that said potential switching device (Vbb) is controlled by timing pulses for selecting said word line (WL).
Claim 7
Dependent Claim
25 words
A memory according to claim 3, characterized in that said potential switching device (Vbb) is controlled by timing pulses for selecting said word line (WL).
Claim 8
Dependent Claim
25 words
A memory according to claim 4, characterized in that said potential switching device (Vbb) is controlled by timing pulses for selecting said word line (WL).
References Cited (Backward Citations)
No citation records indexed.
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