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EP0579566A2
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High-density dram structure on SOI
Assignee: International Business Machines Corp
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Filing: 1993-05-05
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Granted: —
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Expires: 2013-05-05
Abstract
Abstract A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in Figure 1a is rearranged to the shared-gate, double-bit array shown schematically in Figure 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells. The polysilicon layer (40) serves both as a substrate plate electrode for the capacitor and as a channel layer for the vertical transfer transistor with gate (50).
Inventors
- 👤 Chang-Ming Hsieh
- 👤 Louis L.C. Hsu
- 👤 Seiki Ogura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:34
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/34
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
221 words
An integrated circuit cell for dynamic random access memories, comprising in combination: a silicon-on-oxide wafer comprised of an oxide layer on the upper surface of an underlying support wafer and a silicon source layer on the upper surface of said oxide layer; a capacitor trench extending through said silicon source layer and said oxide layer and into said underlying support wafer; a first capacitor plate layer formed conformally on the wall of said capacitor trench, said capacitor plate layer extending to and connected with said silicon source layer; a capacitor dielectric layer formed on said polysilicon capacitor plate layer; a silicon channel layer formed conformally over said capacitor dielectric layer and overlying a region of said patterned silicon source layer, said silicon channel layer forming a second capacitor plate and as well as a channel layer; a polysilicon drain layer overlying said silicon channel layer in said region where said silicon channel layer overlays said silicon source layer; a vertical opening extending through silicon source layer, said silicon channel layer, and said polysilicon drain layer forming a wall surface in the region where the layers overlay one another with an edge in each layer respectively aligned vertically along said wall surface; a gate dielectric covering said wall surface; and a vertical gate in said opening in contact with said gate dielectric.
Claim 2
Dependent Claim
27 words
An integrated circuit cell for dynamic random access memories as in claim 1, further including an isolation dielectric layer formed on the wall of said capacitor trench.
Claim 3
Dependent Claim
22 words
An integrated circuit cell for dynamic random access memories as in claim 1, wherein said capacitor dielectric layer is an oxide-nitride composite.
Claim 4
Dependent Claim
21 words
As integrated circuit cell for dynamic random access memories as in claim 1, wherein said capacitor dielectric layer is an oxide.
Claim 5
Dependent Claim
21 words
An integrated circuit cell for dynamic random access memories as in claim 1, wherein said gate dielectric is an oxide-nitride composite.
Claim 6
Dependent Claim
20 words
An integrated circuit cell for dynamic random access memories as in claim 1, wherein said gate dielectric is an oxide.
Claim 7
Dependent Claim
34 words
An integrated circuit cell for dynamic random access memories as in claim 1, further including: a substrate contract region in said epitaxial silicon layer; and a bit-line contact region in said polysilicon drain layer.
Claim 8
Dependent Claim
25 words
An integrated circuit cell for dynamic random access memories as in claim 1, wherein said silicon channel layer is a low temperature epitaxially grown layer.
Claim 9
Dependent Claim
23 words
An integrated circuit cell for dynamic random access memories as in claim 1, wherein said silicon channel is a solid-phase recrystallized amorphous silicon.
Claim 10
Dependent Claim
310 words
A pair of integrated circuit, shared gate, cells for dynamic random access memories, comprising in combination: a silicon-on-oxide wafer comprised of an oxide layer on the upper surface of an underlying support wafer and a silicon source layer on the upper surface of said oxide layer; a pair of capacitor trenches extending through said silicon source layer and said oxide layer and into said underlying support wafer; a first capacitor plate layer formed conformally on the wall of each of said pair of said capacitor trenches over said isolation oxide, said capacitor plate layer extending to and connected with said silicon source layer; a capacitor dielectric layer formed on said polysilicon capacitor plate layer; a silicon channel layer formed conformally over said capacitor dielectric layer and overlying a region of said silicon source layer, said silicon layer forming a second capacitor plate and a channel layer; a polysilicon drain layer overlying said silicon channel layer in said region where said silicon channel layer overlays said silicon source layer; a vertical opening extending through silicon source layer, said silicon channel layer, and said polysilicon drain layer forming a pair of facing vertical wall surfaces in the region where the layers overlay one another with an edge in each layer respectively aligned vertically along said pair of facing vertical wall surfaces; said silicon channel layer extending from one of said facing wall surfaces forming the channel layer and the second capacitor plate layer for one cell of said pair of integrated circuit cells and said silicon channel layer extending from the other of said facing wall surfaces forming the channel layer and the second capacitor plate layer for the other cell of said pair of integrated circuit cells; a gate dielectric covering said pair of facing vertical wall surfaces; and a vertical gate in said opening in contact with said gate dielectric.
Claim 11
Dependent Claim
55 words
A pair of integrated circuit, shared gate, cells for dynamic random access memories as in claim 10, further including: a substrate contact region in said silicon channel layer common to said pair of integrated circuit cells; and a bit-line contact region in said polysilicon drain layer extending from said one of said facing wall surfaces.
Claim 12
Independent Claim
226 words
A method of forming an integrated circuit cell for dynamic random access memories, comprising the steps of: patterning a silicon source layer on a silicon-on-oxide wafer comprised of an oxide layer on the upper surface of an underlying support wafer; etching a capacitor trench that extends through said patterned silicon source layer and said oxide layer and into said underlying support wafer; conformally depositing a first capacitor plate layer on the wall of said capacitor trench, said first capacitor plate layer extending to and connected with said silicon source layer; forming a capacitor dielectric layer on said first capacitor plate layer; conformally forming an silicon channel layer over said capacitor dielectric layer and overlying a region of said silicon channel layer, said silicon channel layer forming a second capacitor plate and a channel layer; depositing a polysilicon drain layer overlying said silicon channel layer in said region where said silicon channel layer overlays said silicon source layer; etching a vertical opening extending through silicon source layer, said silicon channel layer, and said polysilicon drain layer, said vertical opening forming a wall surface in the region where the layers overlay one another with an edge in each layer respectively aligned vertically along said wall surface; forming a gate dielectric covering said wall surface; and forming a vertical gate in said opening in contact with said gate dielectric.
Claim 13
Independent Claim
306 words
A method of forming a pair of integrated circuit, shared gate, cells for dynamic random access memories, comprising in combination: patterning a silicon-on-oxide wafer comprised of an oxide layer on the upper surface of an underlying support wafer; etching a pair of capacitor trenches that extend through said patterned silicon source layer and said oxide layer and into said underlying support wafer; conformally depositing a first capacitor plate layer on the wall of each of said pair of said capacitor trenches, said first capacitor plate layer extending to and connected with said silicon source layer; forming a capacitor dielectric layer on said polysilicon capacitor plate layer; forming an silicon channel layer conformally over said capacitor dielectric layer and overlying a region of said silicon source layer, said silicon channel layer forming a second capacitor plate and a channel layer; forming a polysilicon drain layer overlying said silicon channel layer in said region where said silicon channel layer overlays said silicon layer; etching a vertical opening extending through silicon source layer, said silicon channel layer, and said polysilicon drain layer forming a pair of facing vertical wall surfaces in the region where the layers overlay one another with an edge in each layer respectively aligned vertically along said pair of facing vertical wall surfaces, said silicon channel layer extending from one of said facing wall surfaces forming the channel layer and the second capacitor plate layer for one cell of said pair of integrated circuit cells and said silicon channel layer extending from the other of said facing wall surfaces forming the channel layer and the second capacitor plate layer for the other cell of said pair of integrated circuit cells; forming a gate dielectric covering said pair of facing vertical wall surfaces; and forming a vertical gate in said opening in contact with said gate dielectric.
References Cited (Backward Citations)
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