EP0030856B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Charge-pumping semiconductor memory cell comprising a charge-storage region and memory device using such a cell
Assignee: Fujitsu Ltd
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Filing: 1980-12-12
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Granted: 1984-03-21
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Expires: 2000-12-12
Abstract
No abstract record available.
Inventors
- 👤 Junji Sakurai
- 👤 Nobuo Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:55
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/35; H; H10; H10B; H10B12/00; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858; H10D86/00; H10P; H10P95/00; H10P95/40; H10P95/402
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
134 words
A charge pumping semiconductor memory cell comprising a semiconductor substrate (3) of one conductivity type, a charge storage region (2), of opposite conductivity type to the semiconductor substrate, on or in the substrate, a source (6) and a drain (7) on or in the charge storage region, a gate (8), on a gate insulator layer (5), on the charge storage region and separating the source and drain, said charge storage region being electrically floating and for storing charge carriers, characterised in that a region (1) with an introduced plurality of recombination centres is provided in the charge storage region separate from the source and the drain, and beneath a zone in which a channel of the cell is generated, to capture minority charge carriers generated under said gate whereby charge pumping efficiency is increased.
Claim 2
Dependent Claim
134 words
A charge pumping semiconductor memory cell comprising a semiconductor substrate (3) of one conductivity type, a charge storage region (2), of opposite conductivity type to the semiconductor substrate, on or in the substrate, a source (6) and a drain (7) on or in the charge storage region, a gate (8), on a gate insulator layer (5), on the charge storage region and separating the source and drain, said charge storage region being electrically floating and for storing charge carriers, characterised in that a region (1) with an introduced plurality of recombination centres is provided in the charge storage region separate from the source and the drain, and beneath a zone in which a channel of the cell is generated, to capture minority charge carriers generated under said gate whereby charge pumping efficiency is increased.
Claim 3
Dependent Claim
100 words
A cell as claimed in claim 1, further characterised in that there is provided a transistor with a channel of a conductivity type different from that of said memory cell comprising an additional source or an additional drain (11), on or in the semiconductor substrate, and an additional gate (12), on a gate insulator layer, on the semiconductor substrate, separating the additional source or additional drain and the charge storage region, which transistor can be placed in an ON condition for erasing information held in the memory cell in the form of stored charge carriers (Fig. 5, 6 or 7).
Claim 4
Dependent Claim
58 words
A cell as claimed in claim 2, wherein the transistor comprises also an additional drain or an additional source (10) provided on or in the semiconductor substrate in electrical contact with the charge storage region (2), the said additional gate separating the additional source or additional drain and the additional drain or additional source (Fig. 5 or 7).
Claim 5
Dependent Claim
52 words
A cell as claimed in claim 2, wherein the additional gate (12) is so placed as to electrically contact the charge storage region (2), which region acts as an additional drain or an additional source of the transistor in relation to the additional gate and additional source or additional drain (Fig. 6).
Claim 6
Dependent Claim
79 words
A semiconductor memory cell as claimed in claim 2, 3 or 4, further comprising an area (13) of the same conductivity type as the source and drain of claim 1, in the neighborhood of the additional source or the additional drain (11) of claim 2, and on or in the substrate, in electrical contact with the additional source or additional drain of claim 2, connecting the additional source or additional drain of claim 2 to the substrate (Fig. 7).
Claim 7
Dependent Claim
23 words
A semiconductor memory device, characterised by a plurality of semiconductor memory cells each as claimed in any one of claims 1 to 5.
Claim 8
Dependent Claim
26 words
A device as claimed in claim 6, further comprising a control circuit, an address circuit, a writing circuit, a reading circuit, and an information refresh circuit.
References Cited (Backward Citations)
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