Method of forming an SOI structure with a DRAM

Claim 1

A method of forming a DRAM having a memory cell area and a peripheral transistor area, said memory cell area comprising a trench capacitor, said method comprising the following steps: patterning one of the surfaces of a silicon substrate (31) and forming a first gate insulator (32) therein, forming a first gate electrode (43a,43b) on the gate insulator at the peripheral transistor area, forming a first insulating layer (50) over said one of the surfaces of the silicon substrate (31), forming a connection hole (44) in said first insulating layer (50) at the memory cell area and filling a conductive material (45) into the connection hole, forming a second insulating layer (51) over said first insulating layer (50), forming a groove (46) in the second insulating layer and forming a trench capacitor function portion (47,48) to the groove wherein the trench capacitor function portion is connected to the conductive material in the connection hole, bonding another substrate over the second insulating layer, on which the trench capacitor is formed, polishing the other surface of said silicon substrate (31) to form a first silicon portion at the peripheral transistor area and a second silicon portion at the memory cell area, forming a second gate electrode (49a,49b) over the first silicon portion which functions as double-gate transistor with the first gate electrode, and forming a third gate electrode (49c) over the second silicon portion which is connected with the trench capacitor.