CMOS-transistor and one-capacitor dram cell and fabrication process therefor

Claim 1

A memory cell structure for a dynamic semi­conductor memory array of the type including pairs of wordlines having a first wordline for transmitting a first wordline signal manifesting first and second signal levels and a second word­line for transmitting a second wordline signal manifesting two signal levels complementary to said first and second signal levels of said first wordline signal, said memory array further including bit lines, said memory cell structure (e.g. 38 in Fig. 1) being connected between a bit line (34) and a pair of wordlines (26, 28) of said memory array and comprising an NMOS type transistor device (18) including first, second and gate electrodes, a PMOS type transistor device (12) including first, second and gate electrodes, and a storage capacitor (30) wherein said first electrode of said NMOS type transistor device is connected to said first electrode of said PMOS type transistor device and to a bit line of said memory array, and said second electrode of said NMOS type transistor device is connected to said second electrode of said PMOS type transistor device and to said storage capacitor, said gate electrode (18) of said NMOS type tran­sistor device is connected to said first wordline (26) of said pair and said gate electrode (20) of said PMOS type transistor device is connected to said second wordline (28) of said pair, said NMOS and PMOS type transistor devices both being turned off in response to a first signal level on said first wordline and said complementary signal level thereof on said second wordline, and said NMOS and PMOS type transistor devices being both turned on in response to a second signal level on said first wordline and said complementary signal level thereof on said second wordline, and wherein said bit line is electrically connected to said storage capacitor and charge is stored into and read out from said storage capacitor in response to said NMOS and PMOS type transistor devices being turned on and off by said signals on said wordlines.

Claim 8

The method for fabricating a memory cell for a semiconductor memory array comprising the steps of: Step (1) dispose an epitaxial layer on a semicon­ductor substrate and reactive ion etch a trench into the said epitaxial layer and substrate, Step (2) form a composite oxide/nitride/oxide storage insulator layer on the walls inside said trench, Step (3) fill said trench with polysilicon and planarize, Step (4) form a retrograde n-well in said epitaxial layer by a surface impurity implant and a deep impurity implant, Step (5) grow gate oxide and deposit polysilicon gate material for a PMOS type device and deposit an oxide film insulator layer over the PMOS gate and lithographically pattern said oxide film layer, Step (6) implant dopants into said n-well to provide graded source/drain junctions for PMOS and NMOS transistor devices, respectively, Step (7) open the surfaces of said source/drain regions for silicide formation wherein said gate element is protected from said silicide by said oxide film insulator layer formed in step (5), Step (8) form a lightly doped silicon film over said silicide, gate oxide and isolation regions wherein said lightly doped silicon film is deposited in polycrystalline structure and recrystallized by beam annealing, Step (9) define the NMOS type transistor device active area and grow thin NMOS gate oxide, Step (10) adjust channel threshold voltages by an impurity implant. Step (11) deposit polysilicon NMOS type transistor device gate material and pattern, Step (12) form oxide spacer regions on said NMOS gate electrode edges, Step (13) implant dopants to obtain source/drain junctions for a transfer device and grow oxide to cover the device.

Claim 9

The method for fabricating a memory cell for a semiconductor memory array comprising the steps of: Step (1) dispose an epitaxial layer on a semicon­ductor substrate and reactive ion etch a trench into the said epitaxial layer and substrate, Step (2) form a composite oxide/nitride/oxide storage insulator layer on the walls inside said trench, Step (3) fill said trench with polysilicon and planarize, Step (4) form a retrograde n-well in said epitaxial layer by a surface impurity implant and a deep impurity implant, Step (5) grow gate oxide and deposit polysilicon gate material for a PMOS type device and deposit an oxide film insulator layer over the PMOS gate and lithographically pattern said oxide film layer, Step (6) implant dopants into said n-well to provide graded source/drain junctions for PMOS and NMOS transistor devices, respectively, Step (7) open the surfaces of said source/drain regions for silicide formation wherein said gate element is protected from said silicide by said oxide film insulator layer formed in step (5), Step (8) form a lightly doped silicon film over said silicide, gate oxide and isolation regions wherein said lightly doped silicon film is deposited in polycrystalline structure and recrystallized by beam annealing, Step (9) define the NMOS type transistor device active area and grow thin NMOS gate oxide, Step (10) adjust channel threshold voltages by an impurity implant. Step (11) deposit polysilicon NMOS type transistor device gate material and pattern, Step (12) form oxide spacer regions on said NMOS gate electrode edges, Step (13) implant dopants to obtain source/drain junctions for a transfer device and grow oxide to cover the device.

Claim 11

The method of fabricating a memory cell according to claims 7 or 8 wherein said lightly doped silicon film is deposited in polysilicon structure and the grain boundary traps are inactive by hydrogen passivation treatment.

Claim 12

The method of fabricating a memory cell according to at least one of claims 7 to 9 wherein said lightly doped silicon film is deposited amorphous film which is converted to single crystal by thermal treatment and with crystalline seeds of said silicided p+ source/drain region.

Claim 13

The method of fabricating a memory cell according to at least one of claims 7 or 9 wherein said lightly doped silicon is deposited in polycry­stalline structure and the p-type doping level is adjusted to provide a high threshold voltage.