EP0642173B1
Expired / Lapsed
EP
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Semiconductor element and semiconductor memory device using the same
Assignee: Hitachi Ltd
•
Filing: 1994-08-12
•
Granted: 1999-07-14
•
Expires: 2014-08-12
Abstract
No abstract record available.
Inventors
- 👤 Kazuo Yano
- 👤 Tomoyuki Ishii
- 👤 Takashi Hashimoto
- 👤 Koichi Seki
- 👤 Masakazu Aoki
- 👤 Takeshi La Kabina De Amichi 301 Sakata
- 👤 Yoshinobu Nakagome
- 👤 Kan Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:35
CPC Classifications
H; H10; H10B; H10B12/00; B; B82; B82Y; B82Y10/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/06; G11C16/10; G11C16/26; G11C16/28; H10B41/00; H10B41/20; H10B41/40; H10B41/42; H10B41/49; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/40; H10D30/402; H10D30/60; H10D30/68; H10D30/688; H10D30/6891; H10D30/6892; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; G11C2216/00; G11C2216/02; G11C2216/06; G11C2216/08; H10D30/62; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
192 words
A semiconductor element, comprising a source region (1, 19, 35) constituting a source of
said semiconductor element; a drain region (2, 20, 36) constituting a drain of said
semiconductor element; an effective channel region (3, 21, 33, 39, 46) provided
between said source region (1, 19, 35) and said drain region
(2, 20, 36) for interconnection thereof; a gate electrode (4, 22, 31; 32, 37; 38) connected to
said effective channel region (3, 21, 33, 39) through a gate
insulation film (5, 23, 40, 49; 50; 53) interposed between
said gate electrode and said effective channel region; and a level node (7, 24, 34, 47) formed between said source
region and said drain region in the vicinity of a current
path (6) in said effective channel region for capturing at
least one carrier, characterised in that effective capacitance (Cgc) between said gate
electrode and said effective channel region is set as to satisfy
a condition given by the following inequality expression: 1/C gc > kT/q 2 wherein C gc represents said effective capacitance, k represents Boltzmann's constant, T represents an operating temperature in degree
Kelvin, and q represents charge of an electron.
Claim 2
Dependent Claim
23 words
A semiconductor element according to claim 1, wherein
said effective channel region (3, 21, 33, 39, 46) is formed
of a polycrystalline semiconductor.
Claim 3
Dependent Claim
46 words
A semiconductor element according to claim 1 or 2,
wherein said effective capacitance (C gc ) between said gate
electrode (4, 22, 31; 32, 37; 38) and said effective channel
region (3, 21, 33, 39, 46) is set at a value not greater than
6 aF.
Claim 4
Dependent Claim
77 words
A semiconductor element according to any of claims 1 to
3, said effective channel region (3, 21, 33, 39, 46) and said
source region (1, 19, 35) being each formed by a semiconductor
thin film, wherein a portion of said source region (1, 19, 35) at
which said source region (1, 19, 35) is to be connected to a
wire has a film thickness greater than that of said effective
channel region (3, 21, 33, 39, 46).
Claim 5
Dependent Claim
46 words
A semiconductor element according to any of claims 1 to
4, wherein a periphery of said effective channel region (3,
21, 33, 39, 46) is covered with a material having a dielectric
constant smaller than that of said effective channel region
(3, 21, 33, 39, 46).
Claim 6
Dependent Claim
42 words
A semiconductor element according to any of claims 1 to
5, wherein said level node is formed as a carrier confinement
region (24); and a potential barrier (25) is provided between
said carrier confinement region (24) and said effective channel
region (21).
Claim 7
Dependent Claim
65 words
A semiconductor element according to claim 6, wherein
total capacitance (C tt ) existing around said carrier confinement
region (24) is set as to satisfy a condition given by
the following inequality expression: q 2 /2C tt > kT where C tt represents said total capacitance, k represents Boltzmann's constant, T represents an operating temperature in degree
Kelvin, and q represents charge of an electron.
Claim 8
Dependent Claim
22 words
A semiconductor element according to claim 6 or 7
wherein said effective channel region (21) is provided on an
insulation film (25).
Claim 9
Dependent Claim
50 words
A semiconductor element according to claim 6 or 7, said
gate electrode including a first gate electrode (31) and a
second gate electrode (32); and said effective channel region (33) and said carrier confinement
region (34) being disposed between said first gate
electrode (31) and said second gate electrode (32).
Claim 10
Dependent Claim
45 words
A semiconductor element according to claim 6 or 7,
wherein said gate electrode includes a first gate electrode
(37) and a second gate electrode (38); and said second gate electrode (38) is disposed between said
first gate electrode (37) and said effective channel region
(39).
Claim 11
Dependent Claim
26 words
A semiconductor element according to any of claims 6 to
10, wherein an island of crystal thin film is used for forming
said carrier confinement region.
Claim 12
Dependent Claim
60 words
A semiconductor element according to any of claims 1 to
3 wherein said level node (7) is located within said effective
channel region at a position so close to said current
path that an electric field effect is exerted onto said current
path by said level node and wherein said current path
has a thickness of 10 nm at maximum.
Claim 13
Dependent Claim
38 words
A semiconductor element according to claim 12, wherein
said effective channel region is formed of a polycrystalline
semiconductor material in a thickness not greater than 100
nm, and said level node is formed by a crystal grain boundary.
Claim 14
Independent Claim
82 words
A method of operating a semiconductor element according
to any of claims 1 to 13, wherein when a potential difference
between said gate electrode (4, 22, 31; 32, 37; 38) and said
source (1, 19, 35) is increased and decreased repetitively
while holding constant a voltage between said drain (2, 20,
36) and said source (1, 19, 35), conductance between said
gate electrode (4, 22, 31; 32, 37; 38) and said source (1,
19, 35) exhibits a hysteresis at a room temperature.
Claim 15
Dependent Claim
45 words
A semiconductor memory device, comprising: a plurality of memory cells (MPn, MMn) each including a
semiconductor element as set forth in any of claims 1 to 13,
wherein said plurality of memory cells (MPn, MMn) are controlled
via word wires (W) and data wires (D).
Claim 16
Dependent Claim
213 words
A method of operating a semiconductor memory device according
to claim 15, wherein when a potential difference between said gate electrode
(4, 22, 31; 32, 37; 38) and said source (1, 19, 35) or said
drain (2, 20, 36) of said memory cell is represented by V gs , said potential difference (V gs) is set to a voltage (v g1 )
for writing logic "1" to thereby rise a threshold voltage of
a selected one of said plurality of memory cells (MPn, MMn),
and said potential difference (V gs ) of said selected memory
cell is externally set to a voltage (V g0 ) for writing logic
"0" which is lower than said logic "1" writing voltage (v g1 )
to thereby lower the threshold voltage of said memory cell,
and wherein a potential difference (V gs ) between said logic
"1" writing voltage (V g1 ) and said logic "0" writing voltage
(V g0 ) is applied to said selected memory cell (MP, MM) as
said potential difference (V gs ) with a potential difference
being additionally applied to said selected memory cell between
said source (1, 19, 35) and said drain (2, 20, 36)
thereof, to thereby read out information by detecting a
drain-source current of said selected memory cell.
Claim 17
Dependent Claim
72 words
A method of operating a semiconductor memory device according to claim 16,
wherein a circuit for controlling rising or lowering of said
threshold voltage and a circuit for detecting said drain-source current
are constituted by field-effect transisitors (FETs) formed in
a surface area of a monocrystalline semiconductor substrate
(14), and wherein said plurality of said memory cells (MPn, MMn)
are formed on said circuits (FETs) with an insulation film
being interposed therebetween.
Claim 18
Dependent Claim
58 words
A semiconductor memory device according to claim 15,
wherein the gate electrode of each of said semiconductor elements
of said memory cells (MMn) is connected to a word wire
(W); and the source-drain path of each of said semiconductor
elements of said memory cells (MMn) is connected between a
data wire (D) and an operating potential point (P).
Claim 19
Dependent Claim
56 words
A semiconductor memory device according to claim 15,
wherein the gate electrode of each of said semiconductor elements
of said memory cells (MMn) is connected to said drain;
and wherein the source-drain path of each of said semiconductor
elements of said memory cells (MMn) is connected between
a word wire (W) and a data wire (D).
Claim 20
Dependent Claim
69 words
A semiconductor memory device according to claim 18
wherein each of said plurality of memory cells further includes
a switching element (M25), a source-drain path of each
of said switching elements (M25) being connected in series to
each of said semiconductor elements between the data wire (D)
and the operating potential point (P); and gate of each of said switching elements (M25) being controlled
via a word wire (W).
Claim 21
Dependent Claim
143 words
A semiconductor memory device according to claim 15,
wherein each memory cell includes a first semiconductor element
(MM31) having a source-drain path connected between a
first operating potential point (C) and a first node (N31);
and a second semiconductor element (MM32) having a source-drain
path connected between said first node (N31) and a second
operating potential point (P); wherein each of said memory cells is capable to store as
data of logic "1" a state in which a threshold voltage of
said first semiconductor element (MM31) is low while a
threshold voltage of said second semiconductor element (MM32)
is high; and wherein each of said memory cells is capable to store as
data of logic "0" a state in which the threshold voltage of
said first semiconductor element (MM31) is high while the
threshold voltage of said second semiconductor element (MM32)
is low.
Claim 22
Dependent Claim
139 words
A semiconductor memory device according to claim 15,
wherein each memory cell includes a first semiconductor element
(MM41) having a source-drain path connected between a
first data wire (D) and an operating potential point (P); and
a second semiconductor element (MM42) having a source-drain
path connected between a second data wire (Dn) and the operating
potential point (P); wherein each memory cell is capable to store as data of
logic "1" a state in which a threshold voltage of said first
semiconductor element (MM41) is low while a threshold voltage
of said second semiconductor element (MM42) is high; and
wherein each memory cell is capable to store as data of logic
"0" a state in which the threshold voltage of said first
semiconductor element (MM41) is high while the threshold
voltage of said second semiconductor element (MM42) is low.
Claim 23
Dependent Claim
82 words
A semiconductor memory device according to claim 22,
wherein each memory cell further includes first and second
switching elements (M45, M46), said first switching element
(M45) having a source-drain path connected in series to said
first semiconductor element (MM41) between said first data
wire (D) and said operating potential point (P); and said second switching element (M46) having a source-drain
path connected in series to said second semiconductor
element (MM42) between said second data wire (Dn) and said
operating potential point (P).
Claim 24
Dependent Claim
120 words
A semiconductor memory device according to claim 15, including
a plurality of memory cells each including a first
semiconductor element (MM51) having a source-drain path connected
between a first data wire (MD51) and an operating potential
point; a plurality of dummy cells each including a second semiconductor
element (MM54) having a source-drain path connected
between a second data wire (MD52) and said operating potential
point; and a differential amplifier (MA51) comprising a first input
terminal being driven by a signal on said first data wire
(MD51) and a second input terminal being driven by a signal
on said second data wire (MD52); wherein said memory cell is
capable to output data by reading an output signal of said
differential amplifier.
Claim 25
Dependent Claim
109 words
A semiconductor memory device according to claim 24,
further comprising a first amplifier circuit (PA51) connected
to said first data wire (D); a first main data wire (MD51) to which output of said
first amplifier circuit (PA51) is connected; said first input terminal of said differential amplifier
(MA51) being driven by a signal on said first main data wire
(MD51); a second amplifier circuit (PA52) connected to said
second data wire; and a second main data wire (MD52) to which
output of said second amplifier circuit (PA52) is connected; said
second input terminal of said differential amplifier (MA51)
being driven by a signal on said second main data wire.
Claim 26
Dependent Claim
34 words
A semiconductor memory device according to claim 25,
wherein said second amplifier circuit (PA52) is designated to
have an output current driving capability which is smaller
than that of said first amplifier circuit (PA51).
Claim 27
Dependent Claim
100 words
A semiconductor memory device according to claim 15,
comprising first and second semiconductor elements (MM70)
each including an electrically conducting region (B) located
in the vicinity of the channel in addition to the gate electrode;
wherein the conducting region (B) of said first semiconductor
element (MM70) and that of said second semiconductor
element (MM70) is in a mutually conductive state; and
wherein positional relationship between said conducting regions
and said effective channel regions is so set that potentials
of channels of said first and second semiconductor
elements can change simultaneously in response to change in
potential of said conducting regions.
Claim 28
Dependent Claim
22 words
A data processing apparatus, comprising a processor and
a storage, said storage including a nonvolatile semiconductor
memory device according to claim 15.
References Cited (Backward Citations)
No citation records indexed.
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